欢迎访问ic37.com |
会员登录 免费注册
发布采购

TSL2568 参数 Datasheet PDF下载

TSL2568图片预览
型号: TSL2568
PDF下载: 下载PDF文件 查看货源
内容描述: 光 - 数字转换器 [LIGHT-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 36 页 / 395 K
品牌: TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
 浏览型号TSL2568的Datasheet PDF文件第1页浏览型号TSL2568的Datasheet PDF文件第2页浏览型号TSL2568的Datasheet PDF文件第3页浏览型号TSL2568的Datasheet PDF文件第4页浏览型号TSL2568的Datasheet PDF文件第6页浏览型号TSL2568的Datasheet PDF文件第7页浏览型号TSL2568的Datasheet PDF文件第8页浏览型号TSL2568的Datasheet PDF文件第9页  
TSL2568, TSL2569
LIGHT-TO-DIGITAL CONVERTER
TAOS091D − DECEMBER 2008
NOTES: 2. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible 640 nm LEDs
and infrared 940 nm LEDs are used for final product testing for compatibility with high-volume production.
3. The 640 nm irradiance E
e
is supplied by an AlInGaP light-emitting diode with the following characteristics: peak wavelength
λp
= 640 nm and spectral halfwidth
Δλ½
= 17 nm.
4. The 940 nm irradiance E
e
is supplied by a GaAs light-emitting diode with the following characteristics: peak wavelength
λp
= 940 nm and spectral halfwidth
Δλ½
= 40 nm.
5. Integration time T
int
, is dependent on internal oscillator frequency (f
osc
) and on the integration field value in the timing register as
described in the
Register Set
section. For nominal f
osc
= 735 kHz, nominal T
int
= (number of clock cycles)/f
osc
.
Field value 00: T
int
= (11
×
918)/f
osc
= 13.7 ms
Field value 01: T
int
= (81
×
918)/f
osc
= 101 ms
Field value 10: T
int
= (322
×
918)/f
osc
= 402 ms
Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01),
and 322/322 = 1 (field value 10).
6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also
by a 2-count offset.
Full scale ADC count value = ((number of clock cycles)/2 − 2)
Field value 00: Full scale ADC count value = ((11
×
918)/2 − 2) = 5047
Field value 01: Full scale ADC count value = ((81
×
918)/2 − 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached
for 131074 clock cycles, which occurs for T
int
= 178 ms for nominal f
osc
= 735 kHz.
7. Low gain mode has 16
y
lower gain than high gain mode: (1/16 = 0.0625).
8. The sensor Lux is calculated using the empirical formula shown on p. 22 of this data sheet based on measured Ch0 and Ch1 ADC
count values for the light source specified. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual
Lux) ratio is estimated based on the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with
fluorescent or incandescent light sources.
AC Electrical Characteristics, V
DD
= 3 V, T
A
= 255C (unless otherwise noted)
PARAMETER
t
(CONV)
f
(SCL)
t
(BUF)
t
(HDSTA)
t
(SUSTA)
t
(SUSTO)
t
(HDDAT)
t
(SUDAT)
t
(LOW)
t
(HIGH)
t
(TIMEOUT)
t
F
t
R
C
i
TEST CONDITIONS
MIN
12
0
10
1.3
0.6
0.6
0.6
0
100
1.3
0.6
25
TYP
100
MAX
400
400
100
UNIT
ms
kHz
kHz
μs
μs
μs
μs
μs
ns
μs
μs
Conversion time
Clock frequency (I
2
C only)
Clock frequency (SMBus only)
Bus free time between start and stop condition
Hold time after (repeated) start condition. After
this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Detect clock/data low timeout (SMBus only)
Clock/data fall time
Clock/data rise time
Input pin capacitance
0.9
35
300
300
10
ms
ns
ns
pF
Specified by design and characterization; not production tested.
The
LUMENOLOGY
r
Company
r
r
www.taosinc.com
Copyright
E
2008, TAOS Inc.
5