PRECISION ANALOG FRONT ENDS
TC500
TC500A
TC510
1
2
3
4
5
6
7
8
TC514
30
20
10
0
1
tINT
0
VREF tDEINT
RINT CINT
VIN (t) dt =
T = MEASUREMENT
PERIOD
∫
RINT CINT
where:
VREF = Reference Voltage
tINT = Signal Integration time (fixed)
tDEINT = Reference Voltage Integration time (variable)
For a constant VIN:
tDEINT
VIN = VREF
tINT
0.1/T
1/T
INPUT FREQUENCY
10/T
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as they are
stable during a measurement cycle.
Aninherentbenefitisnoiseimmunity.Inputnoisespikes
are integrated (averaged to zero) during the integration
periods. Integrating ADCs are immune to the large conver-
sion errors that plague successive approximation convert-
ers in high-noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate. Interference
signals with frequencies at integral multiples of the integra-
tion period are, theoretically, completely removed since the
average value of a sine wave of frequency (1/t) averaged
over a period (t) is zero.
Integrating converters often establish the integration
period to reject 50/60Hz line frequency interference signals.
The ability to reject such signals is shown by a normal mode
rejection plot (Figure 4). Normal mode rejection is limited in
practice to 50 to 65dB, since the line frequency can deviate
by a few tenths of a percent (Figure 3).
Figure 4.. Integrating Converter Normal Mode Rejection
TC500/500A/510/514 CONVERTER OPERATION
The TC500/500A/510/514 incorporates an Auto zero
and Integrator phase in addition to the input signal Integrate
and reference Deintegrate phases. The addition of these
phases reduce system errors and calibration steps, and
shorten overrange recovery time. A typical measurement
cycle uses all four phases in the following order:
(1) Auto zero
(2) Input signal integration
(3) Reference deintegration
(4) Integrator output zero
The internal analog switch status for each of these
phases is summarized in Table 1. This table is referenced
to the Functional Block Diagram on the first page of this data
sheet.
80
70
Auto-Zero Phase (AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging CAZ
(auto-zero capacitor) with a compensating error voltage.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The refer-
ence capacitor is charged to the reference voltage potential
throughSWR. Afeedbackloop,closedaroundtheintegrator
and comparator, charges the CAZ capacitor with a voltage to
compensate for buffer amplifier, integrator and comparator
offset voltages.
t = 0.1 sec
60
50
40
DEV
NORMAL
MODE = 20 LOG
REJECTION
SIN 60 π t (1 ±
60t (1 ±
)
100
DEV
)
30
20
100
DEV = DEVIATION FROM 60 Hz
t = INTEGRATION PERIOD
0.01
0.1
1.0
LINE FREQUENCY DEVIATION FROM 60 Hz (%)
Figure 3. Line Frequency Deviation
TELCOM SEMICONDUCTOR, INC.
3-25
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
