MICROMASTER™ – SYSTEM SUPERVISOR
WITH POWER SUPPLY MONITOR, WATCHDOG
AND BATTERY BACKUP
1
TC70
TC71
Resistor Value Selection
The values of R1 and R2 must be chosen to ensure a
valid low strobe level (V
STL
) on RS when the processor I/O
line is low. The use of 10kΩ,
±5%
tolerance resistors are
recommended. These values result in a nominal strobe level
of 2.83V on RS (min/max of 2.43V/3.24V, assuming
V
DD
= 5.0V
±10%).
Other resistor values can be used, so
long as the additive tolerances of the power supply and
resistor values result in a strobe that falls within V
STH
and
V
STL
under all additive tolerance conditions.
data corruption during power up and power down. The
battery switchover circuit compares V
CC
to the V
BATT
input
and connects VCCO to whichever is higher. Switchover
(V
SW
) occurs when V
CC
is 10mV below V
BATT
as V
CC
falls,
and when V
CC
is 10mV more than V
BATT
as V
CC
rises. The
battery switchover comparator has 20mV of hysteresis to
prevent switch chattering if V
CC
falls very slowly.
2
3
4
5
6
7
Integrated Battery Backup (TC71)
The TC71 differs from the TC70 in that it has a Power
Fail (PF) output instead of a gated chip enable (CEI, CEO).
PF must be externally gated with the decode for the CMOS
RAM or other device to be battery-backed. (Many CMOS
RAMs have both CE and CE enables. In this case, the PF
output can be connected directly to the CE input of the RAM).
PF is high as long as V
CC
is greater than 4.5V nominal.
When V
CC
falls below 4.5V nominal, PF is driven low.
Battery switchover for the TC71 is otherwise identical to that
of the TC70.
External Override Reset Control
A built-in debounce circuit allows a pushbutton switch
(or other electronic reset signal) to be wire-ORed to RS as
an external reset override (Figure 4). The external reset
signal is required to be an active low signal of at least
20msec in duration. Internally, this input is timed to provide
a minimum reset pulse width output of 500msec.
Threshold Detector
The TC71 issues a low-true output on the TDO pin any
time the TDI pin is less than 1.3V and V
CC
is greater than
V
BATT
. The voltage to be monitored is connected to the TDI
input through a simple resistor divider. The threshold detec-
tor can be used to generate an early power fail warning if the
unregulated DC input to the +5V regulator is available for
monitoring.
Supply Monitor Noise Sensitivity
The TC70/71 is optimized for fast response to negative-
going changes in V
DD
. Systems with an inordinate amount
of electrical noise on V
DD
(such as systems using relays),
may require a 0.1µF bypass capacitor to reduce detection
sensitivity. This capacitor should be installed as close to the
TC70/71 as possible to keep the capacitor lead length short.
Integrated Battery Backup (TC70)
The CEO line (TC70) drives the CE input of a CMOS
RAM or other device to be battery-backed. CEO follows CEI
as long as V
CC
is greater than 4.5V nominal. If V
CC
falls
below 4.5V nominal, CEO is driven to the potential of VCCO
thus write protecting the RAM and preventing accidental
TYPICAL APPLICATIONS
Figure 1 shows a full feature implementation of the
TC70; Figure 2 shows the TC71. Resistors R1 and R2 of
Figure 2 set the trip point voltage for the early power fail
warning circuit using the TC71 threshold detector.
WDD
+5V
VCC
VCCO
CEO
VCC
CE
CMOS
RAM
TC70
VBATT
+3V L
I
BATTERY
GND
CEI
+5V
R1
10K
ADDRESS
DECODER
R2
13K
ADDRESS
RS
I/O
RESET
PROCESSOR
RESET
Figure 1. TC70 Typical Application
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5-11
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
