12-BIT
µ
P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
TC7109
TC7109A
INTEGRATOR
SATURATES
ZI
AZ
ZERO INTEGRATOR
PHASE FORCES
INTEGRATOR
OUTPUT TO 0V
1
2
3
4
5
18
LBEN
HBEN
CE/LOAD
19
20
INTEGRATOR OUTPUT
FOR OVERRANGE INPUT
INTEGRATOR OUTPUT
FOR NORMAL INPUT
INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT
NO ZERO
CROSSING
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
AZ
PHASE I
INT
PHASE II
DE
PHASE III
AZ
2048
FIXED
COUNTS
2048
MIN
COUNTS
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO VIN
4096
COUNTS
MAX
AFTER ZERO CROSSING, ANALOG SECTION
WILL BE IN AUTO-ZERO CONFIGURATION
Figure 3. Conversion Timing (RUN/HOLD Pin High)
TEST
17
HIGH-ORDER
BYTE OUTPUTS
B B B
POL OR 12 11 10
3
4
5
6
7
B
9
8
B
8
LOW-ORDER
BYTE OUTPUTS
B B B B B B
7 6 5 4 3 2
B
1
9 10 11 12 13 14 15 16
14 THREE-STATE OUTPUTS
14 LATCHES
6
7
1
GND
12-BIT COUNTER
LATCH
CLOCK
COMP OUT
AZ
INT
DE (±)
ZI
2
STATUS
TO
ANALOG
SECTION
CONVERSION
CONTROL
LOGIC
OSCILLATOR
AND CLOCK
CIRCUITRY
HANDSHAKE
LOGIC
26
22
23
24
25
21
27
SEND
RUN/ OSC OSC OSC BUFF MODE
IN OUT SEL OSC
HOLD
OUT
Figure 4. Digital Section
8
3-99
TELCOM SEMICONDUCTOR, INC.
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
