3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
analog gates close a feedback loop around the integrator
and comparator. This loop permits comparator offset volt-
age error compensation. The voltage level established on
CAZ compensates for device offset voltages. The auto-zero
phase residual is typically 10 µV to 15 µV.
30
20
10
The auto-zero cycle length is 1000 to 3000 clock
periods.
Signal Integration Phase
The auto-zero loop is entered and the internal differen-
+
tial inputs connect to VIN and VIN–. The differential input
t = MEASUREMENT PERIOD
1/t
signal is integrated for a fixed time period. The TC7126A
signal integration period is 1000 clock periods, or counts.
The externally-set clock frequency is Ϭ4 before clocking the
internal counters. The integration time period is:
0
0.1/t
10/t
INPUT FREQUENCY
4
Figure 2. Normal-Mode Rejection of Dual-Slope Converter
tSI
=
ϫ 1000,
fOSC
For a constant VIN:
where fOSC = external clock frequency.
tRI
tSI
VIN = VR
.
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common, VIN– should be tied to analog com-
mon.
Polarity is determined at the end of signal integrate
phase. Thesignbitisatruepolarityindication, inthatsignals
less than 1 LSB are correctly determined. This allows
precision null detection limited only by device noise and
auto-zero residual offsets.
The dual-slope converter accuracy is unrelated to the
integratingresistorandcapacitorvalues, aslongastheyare
stable during a measurement cycle. Noise immunity is an
inherent benefit. Noise spikes are integrated, or averaged,
to zero during integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50 Hz/60 Hz power line period.
Reference Integrate Phase
The third phase is reference integrate, or deintegrate.
VIN– is internally connected to analog common and VIN+ is
connectedacrossthepreviously-chargedreferencecapaci-
tor. Circuitrywithinthechipensuresthatthecapacitorwillbe
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 internal clock periods. The digital
reading displayed is:
ANALOG SECTION
In addition to the basic integrate and deintegrate dual-
slope cycles discussed above, the TC7126A design incor-
porates an auto-zero cycle. This cycle removes buffer
amplifier, integrator, and comparator offset voltage error
termsfromtheconversion. Atruedigitalzeroreadingresults
without external adjusting potentiometers. A complete con-
version consists of three phases:
(1) Auto-zero phase
VIN
1000
(2) Signal integrate phase
(3) Reference integrate phase
VREF
DIGITAL SECTION
Auto-Zero Phase
The TC7126A contains all the segment drivers neces-
sary to directly drive a 3-1/2 digit LCD. An LCD backplane
driver is included. The backplane frequency is the external
clock frequency Ϭ800. For 3 conversions per second the
backplane frequency is 60 Hz with a 5V nominal amplitude.
During the auto-zero phase, the differential input signal
is disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero input condition. Additional
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