3-1/2 DIGIT A/D CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
If the converter and measured system do not share the same
power supply common, as in battery powered applications,
V
IN–
should be tied to Analog Common.
Polarity is determined at the end of signal integration
phase. The sign bit is a “true polarity” indication in that
signals less than 1 LSB are correctly determined. This
allows precision null detection which is limited only by device
noise and Auto Zero residual offsets.
the need for an external reference. Some minor component
changes are required to upgrade existing designs, reduce
power dissipation, and improve the overall performance.
(see Oscillator Components)
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Digital Section
The TC811 contains all the segment drivers necessary
to directly drive a 3-1/2 digit liquid crystal display (LCD). An
LCD backplane driver is included. The backplane frequency
is the external clock frequency divided by 800. For three
conversions/second the backplane frequency is 60Hz with
a 5V nominal amplitude. When a segment driver is in phase
with the backplane signal the segment of “OFF”. An out of
phase segment drive signal causes the segment to be “ON”
or visible. This AC drive configuration results in negligible
DC voltage across each LCD segment. This insures long
LCD display life. The polarity segment driver is “ON” for
negative analog inputs. If V
IN
+ and V
IN
– are reversed then
this indicator would reverse.
Reference Integrate (Deintegrate) Cycle
The reference capacitor, which was charged during the
Auto Zero cycle, is connected to the input of the integrating
amplifier. The internal sign logic insures that the polarity of
the reference voltage is always connected in the phase
which is opposite to that of the input voltage. This causes the
integrator to ramp back to zero at a constant rate which is
determined by the reference potential.
The amount of time required (T
DEINT
) for the integrating
amplifier to reach zero is directly proportional to the ampli-
tude of the voltage that was put on the integrating capacitor
(V
INT
) during the integration cycle:
T
DEINT
=
R
INT
C
INT
V
INT
V
REF
+
V
IN
– V
IN
V
REF
–
TEST Function (TEST)
On the TC811, when TEST is pulled to a logical “HIGH”,
all segments are turned “ON”. The display will read “-1888”.
During this mode the LCD segments have a constant DC
voltage impressed. Do not leave the display in this mode for
more than several minutes. LCD displays may be destroyed
if operated with DC levels for extended periods.
The display FONT and segment drive assignment are
shown in Figure 5.
DISPLAY FONT
The digital reading displayed Is:
Digital Count = 1000
The oscillator frequency is divided by 4 prior to clocking
the internal decade counters. The four phase measurement
cycle takes a total of 4000 counts or 16000 clock pulses. The
4000 count cycle is independent of input signal magnitude
or polarity.
Each phase of the measurement cycle has the following
length:
1) Auto Zero: 300 to 2900 Counts
2) Signal Integrate: 1000 Counts
This time period is fixed. The integration period is:
T
INT
=
4000
f
OSC
= 1000 Counts
1000's
100's
10's
1's
Figure 5. Display FONT and Segment Assignment
Where f
OSC
is the crystal oscillator frequency.
3) Reference Integrate: 0 to 2000 Counts
4) Integrator Output Zero: 11 to 640 Counts
The TC811 can replace the ICL7106/26/36 in circuits
which require both the hold function and a differential
reference. The TC811 offers a greatly improved internal
reference temperature coefficient, which can often eliminate
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HOLD Reading Input (HLDR)
When HLDR is at a logic “HI” the latch will not be
updated. Conversions will continue but will not be updated
until HLDR is returned to “LOW”. To continuously update the
display, connect HLDR to ground or leave it open. This input
is CMOS compatible and has an internal resistance of 70kΩ
(typical) tied to TEST.
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