PRELIMINARY INFORMATION
3-PIN µP RESET MONITORS
1
2
3
4
5
6
7
8
TCM809
TCM810
APPLICATIONS INFORMATION
VCC Transient Rejection
valid to VCC = 0V, a pull-down resistor must be connected
fromRESETtogroundtodischarge straycapacitancesand
hold the output low (Figure 2). This resistor value, though
not critical, should be chosen such that it does not apprecia-
bly load RESET under normal operation (100kΩ will be
suitableformostapplications).Similarly,apull-upresistorto
VCC is required for the TCM810 to ensure a valid high
RESET for VCC below 1.0V.
The TCM809/810 provides accurate VCC monitoring
and reset timing during power-up, power-down, and brown-
out/sag conditions, and rejects negative-going transients
(glitches) on the power supply line. Figure 1 shows the
maximum transient duration vs. maximum negative excur-
sion (overdrive) for glitch rejection. Any combination of
duration and overdrive which lies under the curve will not
generate a reset signal. Combinations above the curve are
detectedasabrownoutorpower-down. Transientimmunity
can be improved by adding a capacitor in close proximity to
the VCC pin of the TCM809/810.
VCC
VCC
TCM809
RESET
V
CC
V
TH
R1
100k
Overdrive
GND
Duration
Figure 2. Ensuring RESET Valid to VCC = 0V
Processors With Bidirectional I/O Pins
400
T
= +25°C
A
Some µP's (such as Motorola 68HC11) have bidirec-
tional reset pins. Depending on the current drive capability
of the processor pin, an indeterminate logic level may result
if there is a logic conflict. This can be avoided by adding a
4.7k resistor in series with the output of the TCM809/810
(Figure 3). If there are other components in the system
which require a reset signal, they should be buffered so as
not to load the reset line. If the other components are
required to follow the reset I/O of the µP, the buffer should
be connected as shown with the solid line.
320
240
160
TCM8xxLM
80
0
TCM8xxR/S/T
10
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
1
1000
100
BUFFER
RESET COMPARATOR OVERDRIVE,
(V - V (mV)
TH
CC
VCC
Figure 1. Maximum Transient Duration vs.
VCC
µP
RESET
VCC
Overdrive for Glitch Rejection at 25°C
TCM809
4.7k
RESET Signal Integrity During Power-Down
RESET
The TCM809 RESET output is valid to VCC = 1.0V.
Below this voltage the output becomes an "open circuit" and
does not sink current. This means CMOS logic inputs to the
µP will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
GND
GND
Figure 3. Interfacing to Bidirectional Reset I/O
TELCOM SEMICONDUCTOR, INC.
5-17
TELCOM [ TELCOM SEMICONDUCTOR, INC ]
