DG417/418/419
Test Circuits
V
O
is the steady state output with the switch on.
+5 V
+15 V
3 V
0 V
t <20 ns
t <20 ns
f
Logic
Input
r
50%
V
V+
D
L
S
"10 V
V
O
t
OFF
Switch
Input
V
S
IN
GND
V
O
R
300 W
C
35 pF
L
L
90%
V–
Switch
Output
0 V
t
ON
–15 V
C
L
(includes fixture and stray capacitance)
Note: Logic input waveform is inverted for switches that have
the opposite logic sense.
R
L
V
= V
S
O
R
+ r
DS(on)
L
Figure 2. Switching Time (DG417/418)
+5 V
+15 V
Logic
3 V
t <20 ns
r
Input
t <20 ns
f
V
V+
L
0 V
S
S
1
D
V
V
V
S1
S2
O
2
V
= V
S2
S1
R
300 W
C
L
L
V
90%
O
35 pF
IN
GND
Switch
Output
0 V
V–
t
D
t
D
C
L
(includes fixture and stray capacitance)
–15 V
Figure 3. Break-Before-Make (DG419)
+5 V
+15 V
V
V+
3 V
t <20 ns
t <20 ns
f
L
r
Logic
Input
50%
S
S
D
1
V
V
S1
S2
V
O
0 V
2
t
t
TRANS
TRANS
R
300 W
C
L
35 pF
L
V
S1
IN
GND
V
01
90%
V–
Switch
Output
10%
V
02
V
–15 V
(includes fixture and stray capacitance)
S2
C
L
R
L
V
= V
S
O
R
L
+ r
DS(on)
Figure 4. Transition Time (DG419)
Siliconix
S-52880—Rev. D, 28-Apr-97
7
TEMIC [ TEMIC SEMICONDUCTORS ]
