TS80C31X2
Table 2. Pin Description for 40/44 pin packages
MNEMONIC
V
SS
Vss1
V
CC
P0.0-P0.7
PIN NUMBER
DIL
20
LCC
22
1
44
43-36
VQFP 1.4
16
39
38
37-30
TYPE
I
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference
Optional Ground:
Contact the Sales Office for ground connection.
Power Supply:
This is the power supply voltage for normal, idle and power-
down operation
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-up when emitting
1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
SS
permits a power-on reset
using only an external capacitor to V
CC.
Address Latch Enable:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory.
Program Store ENable:
The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable:
EA must be externally held low to enable the device
to fetch code from external program memory locations.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier
40
39-32
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
10
11
12
13
14
15
16
17
Reset
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
33
27
O (I)
PSEN
29
32
26
O
EA
XTAL1
XTAL2
31
19
18
35
21
20
29
15
14
I
I
O
Rev. A - Mar. 19, 1999
5
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
