TSC87251G1A
Signal
Name
ECI
MISO
Type
O
I/O
PCA External Clock input
Description
Alternate
Function
P1.2
P1.5
ECI is the external clock input to the 16–bit PCA timer.
SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave
mode, MISO outputs data to the master controller.
MOSI
I/O
SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave
mode, MOSI receives data from the master controller.
INT1:0#
I
External Interrupts 0 and 1.
INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set,
bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set
by a low level on INT1#/INT0#
P0.0:7
P1.0:7
I/O
I/O
Port 0
P0 is an 8–bit open–drain bidirectional I/O port.
Port 1
P1 is an 8–bit bidirectional I/O port with internal pull–ups. P1 provides interrupt capability for
a keyboard interface.
P2.0:7
P3.0:7
PROG#
I/O
I/O
O
Port 2
P2 is an 8–bit bidirectional I/O port with internal pull–ups.
Port 3
P3 is an 8–bit bidirectional I/O port with internal pull–ups.
Programming Pulse input
The programming pulse is applied to this input for programming the on–chip EPROM/
OTPROM.
PSEN#
O
Program Store Enable/Read signal output
PSEN# is asserted for a memory address range that depends on bits RD0 and RD1 in UCON-
FIG0 byte (see Table 13).
RD#
O
Read or 17
th
Address Bit (A16)
Read signal output to external data memory depending on the values of bits RD0 and RD1 in
UCONFIG0 byte (see Table 13).
RST
I
Reset input to the chip
Holding this pin high for 64 oscillator periods while the oscillator is running resets the device.
The Port pins are driven to their reset conditions when a voltage greater than V
IH1
is applied,
whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset by connecting a
capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power–Down mode returns the chip to normal
operation.
RXD
SCL
SCK
SDA
T1:0
I/O
I/O
I/O
I/O
I/O
Receive Serial Data
RXD sends and receives data in serial I/O mode 0 and receives data in serial modes I/O 1, 2 and 3.
I
2
C Serial Clock
SCL outputs the serial clock to slave peripherals.
SPI Serial Clock
SCK outputs clock to the slave peripheral.
I
2
C Serial Data
SDA is the bidirectional
I
2
C
data line.
Timer 1:0 External Clock Inputs
When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.
P1.7
P1.6
P1.6
P3.0
P3.7
A15:8
AD7:0
P3.3:2
P1.7
6
Rev. A
–
September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
