TSC80251G2D
Table 12. SFR Addresses and Reset Values
0/8
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
IPL0
X000 0000
P3
1111 1111
IE0
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
Reserved
Notes:
1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In I
2
C and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in I
2
C mode and 0000 0100 in SPI mode.
3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000 0000 in write mode.
TMOD
0000 0000
SP
(1)
0000 0111
1/9
SBUF
XXXX XXXX
BRL
0000 0000
SSBR
0000 0000
TL0
0000 0000
DPL
(1)
0000 0000
2/A
BDRCON
XXX0 0000
SSCON
(2)
1/9
CH
0000 0000
2/A
CCAP0H
0000 0000
3/B
CCAP1H
0000 0000
4/C
CCAP2H
0000 0000
5/D
CCAP3H
0000 0000
6/E
CCAP4H
0000 0000
7/F
FFh
F7h
B
(1)
0000 0000
CL
0000 0000
ACC
(1)
0000 0000
CCON
00X0 0000
PSW
(1)
0000 0000
T2CON
0000 0000
CMOD
00XX X000
PSW1
(1)
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
CCAP0L
0000 0000
CCAP1L
0000 0000
CCAP2L
0000 0000
CCAP3L
0000 0000
CCAP4L
0000 0000
EFh
E7h
DFh
D7h
CFh
C7h
SADEN
0000 0000
IE1
XX0X XXX0
SADDR
0000 0000
IPL1
XX0X XXX0
IPH1
XX0X XXX0
SPH
(1)
0000 0000
IPH0
X000 0000
BFh
B7h
AFh
WDTRST
1111 1111
P1LS
0000 0000
SSCS
(3)
WCON
XXXX XX00
A7h
9Fh
97h
P1IE
0000 0000
SSDAT
0000 0000
TH1
0000 0000
P1F
0000 0000
SSADR
0000 0000
CKRL
0000 1000
TL1
0000 0000
DPH
(1)
0000 0000
3/B
TH0
0000 0000
DPXL
(1)
0000 0001
4/C
POWM
8Fh
0XXX XXXX
PCON
0000 0000
87h
5/D
6/E
7/F
Rev. A - May 7, 1999
13
TEMIC [ TEMIC SEMICONDUCTORS ]
