TSC80C31/80C51
Serial Port Timing – Shift Register Mode (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz
min max min max min max min max min max min max min max
SYMBOL
TXLXL
PARAMETER
Serial Port Clock Cycle Time
750
563
600
480
480
380
400
300
330
220
250
170
227
140
TQVXH
Output Data Setup to Clock
Rising Edge
TXHQX
TXHDX
TXHDV
Output Data Hold after Clock
Rising Edge
90
0
90
0
65
0
50
0
45
0
35
0
25
0
Input Data Hold after Clock
Rising Edge
Clock Rising Edge to Input Data
Valid
563
450
350
300
250
200
160
Shift Register Timing Waveforms
16
MATRA MHS
Rev. E (14 Jan.97)