TSC87C52
When in mode 2 and 3 (9–bit mode), RI flag is set during stop bit if framing error is enabled or during ninth bit if not
(see Figure 5).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
SMOD1SMOD0
–
POF
GF1
GF0
PD
IDL
To UART framing error control
Figure 3 Framing error block diagram
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start
bit
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 4 Enhanced UART timing diagram in mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start
bit
Data byte
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 5 Enhanced UART timing diagram in mode 2 and 3
Table 4 SCON – Serial Control Register (98h)
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Symbol
Description
Framing Error bit (SMOD0 bit set)
FE
Set by hardware when an invalid stop bit is detected.
Clear to reset the error state, not cleared by a valid stop bit.
Serial Mode bit 0 (SMOD0 bit cleared)
SM0
SM1
SM2
Used with SM1 to select serial mode.
Serial Mode bit 1
Used with SM0 to select serial mode.
Multiprocessor Communication Enable bit
Set to enable multiprocessor communication feature in mode 2 and 3.
Clear to disable multiprocessor communication feature.
MATRA MHS
Rev. C – 10 Sept 1997
8
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
