TSC87C52
+5V
PROGRAM
SIGNALS*
EA/VPP
ALE/PROG
P0.0–P0.7
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
XTAL1
D0–D7
VCC
P1.0–P1.7
P2.0–P2.4
A0–A7
A8–A12
CONTROL
SIGNALS*
4 to 6 MHz
VSS
GND
* See Table 6 for proper value on these inputs
Figure 8 Set–up modes configuration
Programming algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied
during byte programming from 25 to 5.
To program the TSC87C52 the following sequence must be exercised:
D
D
D
D
D
Step 1: Input the valid address on the address lines.
Step 2: Input the appropriate data on the data lines.
Step 3: Activate the combination of control signals.
Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
Step 5: Pulse ALE/PROG 5 times.
Repeat step 1 through 5 changing the address and data for the entire array or until the end of the object file is reached
(see Figure 9).
Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of
the programmed array will ensure reliable programming of the TSC87C52.
To verify the TSC87C52 code the following sequence must be exercised :
D
D
D
D
Step 1: Activate the combination of program signals.
Step 2: Input the valid address on the address lines.
Step 3: Input the appropriate data on the data lines.
Step 4: Activate the combination of control signals.
Repeat step 2 through 4 changing the address and data for the entire array (see Figure 9).
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code
array is well encrypted.
12
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
