TSC87C52
When in mode 2 and 3 (9–bit mode), RI flag is set during stop bit if framing error is enabled or during ninth bit if not
(see Figure 5).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Set FE bit if stop bit is 0 (framing error)
SM0 to UART mode control
SMOD1 SMOD0
–
POF
GF1
GF0
PD
IDL
To UART framing error control
Figure 3 Framing error block diagram
RXD
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
Data byte
RI
SMOD0=X
FE
SMOD0=1
Figure 4 Enhanced UART timing diagram in mode 1
RXD
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
Ninth
bit
Stop
bit
Data byte
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 5 Enhanced UART timing diagram in mode 2 and 3
Table 4 SCON – Serial Control Register (98h)
7
SM0/FE
Symbol
FE
6
SM1
5
SM2
Description
4
REN
3
TB8
2
RB8
1
TI
0
RI
Framing Error bit (SMOD0 bit set)
Set by hardware when an invalid stop bit is detected.
Clear to reset the error state, not cleared by a valid stop bit.
Serial Mode bit 0 (SMOD0 bit cleared)
Used with SM1 to select serial mode.
Serial Mode bit 1
Used with SM0 to select serial mode.
Multiprocessor Communication Enable bit
Set to enable multiprocessor communication feature in mode 2 and 3.
Clear to disable multiprocessor communication feature.
SM0
SM1
SM2
8
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
