TSC87C52
Pin Configuration
P1.0/T2
P1.1/T2EX
P1.2
1
2
3
4
5
6
7
8
9
40 VCC
39 P0.0
38 P0.1
37 P0.2
36 P0.3
35 P0.4
34 P0.5
33 P0.6
32 P0.7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7
27 P2.6
26 P2.5
25 P2.4
24 P2.3
23 P2.2
22 P2.1
21 P2.0
P1.3
6
5
4
3
2
1
44 43 42 41 40
P1.4
7
39
P1.5
P1.6
P0.4/AD4
P1.5
38
8
P0.5/AD5
P1.6
37
9
P1.7
P0.6/AD6
P1.7
10
11
12
13
14
15
16
17
36
RST
P0.7/AD7
RST
35
P3.0/RxD
Reserved
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
EA/VPP
P3.0/RxD 10
P3.1/TxD 11
P3.2/INT0 12
P3.3/INT1 13
P3.4/T0 14
P3.5/T1 15
P3.6/WR 16
P3.7/RD 17
XTAL2 18
34
Reserved
DIP
PLCC/CQPJ
33
32
31
30
29
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
XTAL1 19
VSS 20
44 43 42 41 40 39 38 37 36 35 34
33
1
P1.5
P1.6
P0.4/AD4
32
2
P0.5/AD5
31
3
P1.7
P0.6/AD6
4
30
29
28
27
26
25
24
23
RST
P0.7/AD7
EA/VPP
5
P3.0/RxD
Reserved
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6
Reserved
ALE/PROG
PSEN
Flat Pack
7
8
9
P2.7/A15
P2.6/A14
P2.5/A13
10
11
12 13 14 15 16 17 18 19 20 21 22
Figure 2 TSC87C52 pin configuration
Do not connect Reserved pins.
MATRA MHS
Rev. C – 10 Sept 1997
3
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
