欢迎访问ic37.com |
会员登录 免费注册
发布采购

U2730B-BFSG1 参数 Datasheet PDF下载

U2730B-BFSG1图片预览
型号: U2730B-BFSG1
PDF下载: 下载PDF文件 查看货源
内容描述: L波段下变频器的DAB接收器 [L-Band Down-Converter for DAB Receivers]
分类和应用: 射频和微波射频上变频器射频下变频器微波上变频器微波下变频器
文件页数/大小: 12 页 / 261 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
 浏览型号U2730B-BFSG1的Datasheet PDF文件第2页浏览型号U2730B-BFSG1的Datasheet PDF文件第3页浏览型号U2730B-BFSG1的Datasheet PDF文件第4页浏览型号U2730B-BFSG1的Datasheet PDF文件第5页浏览型号U2730B-BFSG1的Datasheet PDF文件第6页浏览型号U2730B-BFSG1的Datasheet PDF文件第7页浏览型号U2730B-BFSG1的Datasheet PDF文件第8页浏览型号U2730B-BFSG1的Datasheet PDF文件第9页  
U2730B-B
L-Band Down-Converter for DAB Receivers
Description
The U2730B-B is a monolithic integrated L-band down-
converter circuit fabricated in TEMIC’s advanced
UHF5S technology. Combining the functionality of
U2754B-B and U2755B-B in one integrated circuit, it
covers all functions of an L-band down-converter in a
DAB receiver. The device includes a gain-controlled
amplifier, a gain-controlled mixer, an output buffer, a
gain-control block, an L-band oscillator and a complete
frequency syntheziser unit. The frequency syntheziser
block consists of an input buffer for the reference
frequency signal, a reference divider, an LO divider, a
tri-state phase detector, a loop filter amplifier, a lock
detector, a programmable charge pump, a test interface
and a control interface.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D
D
D
D
D
D
D
D
D
Supply voltage: 8.5 V
RF frequency range: 1400 MHz to 1550 MHz
IF frequency range: 150 MHz to 250 MHz
Overall IM3 rejection: > 40 dB
Overall gain control range: typ. 30 dB
DSB noise figure: 9.5 dB
Gain-controlled amplifier
Gain-controlled L-band mixer
On-chip gain-control circuitry
TH
17
AGC 18
Test interface
internal supply voltage for
frequency synthesizer
D
On-chip VCO, typical frequency 1261.568 MHz
D
Internal VCO can be overdriven by an external LO
D
On-chip frequency synthesizer
Fixed LO divider factor: 2464
Four reference divider factors selectable: 32, 35, 36, 48
Tristate phase detector with programmable charge pump
De-activation of tuning output programmable
Lock-status indication
Test interface
VCC1 VCC3 VCC4
3
20
28
VCC2
9
Voltage
stabilizer
GND
6, 7, 8, 21,
22, 23, 24
Block Diagram
IF
19
TMD
TRD
10
11
U
26
25
Lock
detector
14
13
20k
12
Reference counter
RF
NRF
PLCK
PD
VCO
RF counter
2464
Tristate
phase
detector
Programmable
charge pump
(50µA / 200µA)
CD
32/35/36/48
Control interface
4
VREF
5
15
16
NREF
2
C
27
S
14749
TANK REF
Figure 1. Block diagram
Rev. A1, 22-Jul-98
1 (12)
Preliminary Information