U842B
V
Batt
R
1
180
Ω
R
9
220 kΩ
C
1
47
µF
8
7
6
5
C
2
100 nF
U842B
1
R
4
10 kΩ
Switch
INT
Button
WASH
PARK
Figure 3. Basic cicuitry
R
5
47 kΩ
2
3
R
6
10 kΩ
R
11
360
Ω
VR
1
1 kΩ
4
R
7
1.5 kΩ
13288
Variable Debouncing Times
Debouncing is basically done by counting oscillator
clocks starting with the occurance of any input signal.
Caused by the asynchronism of input signal and IC-clock,
the debouncing time may vary in a certain range.
Figure 4 shows the short circuit debouncing as an
example:
During the relay activation, a comparator monitors the
output current at each positive edge of the clock to load
a 3-stage shift register in the case of a detected short cir-
cuit condition i.e., I > 500 mA. With the third edge, the
output stage is disabled. Dependent on the short circuit
occurence the delay time may range from 2 to 3 clock
cycles.
The timing can be adjusted by variation of the external
frequency-determining components ( R/C).
The potentiometer at Pin 4 determines the interval pause,
which can be varied by adjusting the upper charging
threshold of the oscillator. For all other time periods, an
internal voltage divider determines the upper charging
threshold of the oscillator (see figure 2).
Timing
Fixed:
Relay activation time
Dry wiping
Interval pause
Switch-on delay INT
Variable:
Debouncing time INT
Debouncing time WASH
1. pre-wash delay
2. reverse debouncing
Debouncing time PARK
Debouncing time SC
t
5
t
2
=
=
160 1/f
0
896 1/f
0
or 3 cycles
872 1/f
0
8 1/f
0
24 to 32 1/f
0
112 to 128 1/f
0
16 to 32 1/f
0
6 to 8 1/f
0
2 to 3 1/f
0
t
6
=
t
4D
=
t
4
=
t
1
=
t
1.R
=
t
8
=
t
7
=
TELEFUNKEN Semiconductors
Rev. A2, 03-Feb-97
3 (12)
TEMIC [ TEMIC SEMICONDUCTORS ]
