AVPro® 5002R
Dual SCART A/V Switch
DATA SHEET
Auxiliary Audio Operation
The auxiliary port includes stereo audio outputs for a
SCART connector (Aux_Lout,
Aux_Rout)
and a mono
audio output (Aux_Mono). These outputs can choose
between the
Lin/Rin
input pins or the
TV_Lin/TV_Rin
input pins. The audio inputs are switched in concert
with the associated video inputs according to Bits 3-5 in
Register 1.
Internal multiplexers allow the
Aux_Lout
and
Aux_Rout
outputs to be configured into either stereo or mono
audio outputs. The two MSBs of Register 3 control the
stereo/mono selection according to the following table:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Aux_Lout
source
Lin
Lin+Rin
Lin
Rin
Aux_Rout
source
Rin
Lin+Rin
Lin
Rin
such that if register 4 is to be programmed, then
registers 0, 1, 2, 3 and 4 need to be sent. If only
register 2 needs to be programmed, then only registers
0, 1 and 2 data need to be sent. It will support standard
and fast bus speed. The default address of the device
is 1001000x (1001000 for Write and 10010001 for
Read).
The 5002R includes a read register in which the upper
four bits identify the specific chip within the AVPro
®
family. This allows a single application platform and
software to work with a wide variety of AVPro
®
chips.
The ID code for the 5002R is 0001.
Data Transfers
A data transfer starts when the
SDATA
pin is driven
from HIGH to LOW by the bus master while the
SCLK
pin is HIGH. On the following eight clock cycles, the
device receives the data on the
SDATA
pin and
decodes that data to determine if a valid address has
been received. The first seven bits of information are
the address with the eighth bit indicating whether the
cycle is a read (bit is HIGH) or a write (bit is LOW). If
the address is valid for this device, on the falling
SCLK
edge of the eighth bit of data, the device will drive the
SDATA
pin low and hold it LOW until the next rising
edge of the
SCLK
pin to acknowledge the address
transfer. The device will continue to transmit or receive
data until the bus master has issued a stop by driving
the
SDATA
pin from LOW to HIGH while the
SCLK
pin
is held HIGH
Write Operation:
When the read/write bit (LSB) is
LOW and a valid address is decoded, the device will
receive data from the
SDATA
pin. The device will
continue to latch data into the registers until a stop
condition is detected. The device generates an
acknowledge after each byte of data written.
Read Operation:
When the read/write bit (LSB) is
HIGH and a valid address is decoded, the device will
transmit the data from the internal register on the
following eight
SCLK
cycles. Following the transfer of
the register data and the acknowledge from the master,
the device will release the data bus.
Reset:
At power-up the serial port defaults to the states
indicated in boldface type. The device also responds to
the system level reset that is transmitted through the
serial port. When the master sends the address
00000000 followed by the data 00000110, the device
resets to the default condition.
At power-up, these bits default to 00 putting the device
in the stereo mode.
The
Aux_Mono
output is generated through an internal
summing node that combines the signals of the
Aux_Lout
and
Aux_Rout
outputs. All three auxiliary
audio outputs can be muted by setting the MSB in
Register 0. This bit is set high (1) at power-up causing
the outputs to be muted. Setting this bit low (0) enables
all auxiliary audio outputs.
Digital Outputs
The 5002R provides two programmable digital outputs,
DO_0
and
DO_1 (not available on the 48 QFN option).
These pins are general purpose outputs programmed
by setting Bit 0 and 1 in Register 3. Setting the register
bits to 0 puts these outputs in the logic low state.
Setting the register bits to 1 puts the outputs in the logic
high state. Internal pull-up resistors (approximately
17kΩ) are included on these pins.
Serial Port Definition
Internal functions of the device are monitored and
controlled by a standard inter-IC (I
2
C)bus with data
being transferred MSB first on the rising edge of the
clock. The serial port operates in a slave mode only
and can be written to or read from. The device uses 7-
bit addressing, and does not support 10-bit addressing
mode. The write register data is sent sequentially,
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©
2008 TERIDIAN Semiconductor Corporation
Rev 2.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
