AVPro® 5303B
Universal 3-Input A/V Switch Interface
DATA SHEET
TV Function Input
The TV Function feature generally supports three-level
logic signal required for SCART TV Function Switching:
Input Voltage
0-2V
4.5-7V
9.5-12V
TV Function Switching Mode
Broadcast TV
16:9 Peritelevision Reproduction
Normal Peritelevision Reproduction
Serial Port Definition
Internal functions of the device are monitored and
controlled by a standard inter-IC (I
2
C)bus with data
being transferred MSB first on the rising edge of the
clock. The serial port operates in a slave mode only
and can be written to or read from. The device uses
7-bit addressing, and does not support 10-bit
addressing mode. The write register data is sent
sequentially, such that if register 1 is to be
programmed, then registers 0 and 1 need to be sent.
If only register 0 needs to be programmed, then only
registers 0 data needs to be sent. It will support
standard and fast bus speed. The default address
of the device is 1001000x (1001000 for Write and
10010001 for Read).
The 5303B includes a read register in which the upper
four bits identify the specific chip within the AVPro
®
family. This allows a single application platform and
software to work with a wide variety of AVPro
®
chips.
The ID code for the 5303B is 0010.
In the AVPro® 5303B device, the TV Function
feature works in pass through mode only.
The three
inputs, Func1, Func2 and Func3 support the pass
through mode of the TV Function feature
. A 100kΩ
load is recommended for typical operation at the
Func_out pin.
Fast Blanking (FB) Input
The FB1, FB2 and FB3 inputs support two-level logic
signal required for SCART Fast Blanking:
Logic
0
1
Input Voltage
0-0.4V
1-3V
Fast Blanking Mode
CVBS Active
RGB Active
Data Transfers
A data transfer starts when the
SDATA
pin is driven
from HIGH to LOW by the bus master while the
SCLK
pin is HIGH. On the following eight clock cycles, the
device receives the data on the
SDATA
pin and
decodes that data to determine if a valid address has
been received. The first seven bits of information are
the address with the eighth bit indicating whether the
cycle is a read (bit is HIGH) or a write (bit is LOW). If
the address is valid for this device, on the falling
SCLK
edge of the eighth bit of data, the device will drive the
SDATA
pin low and hold it LOW until the next rising
edge of the
SCLK
pin to acknowledge the address
transfer. The device will continue to transmit or receive
data until the bus master has issued a stop by driving
the
SDATA
pin from LOW to HIGH while the
SCLK
pin
is held HIGH
Write Operation:
When the read/write bit (LSB) is
LOW and a valid address is decoded, the device will
receive data from the
SDATA
pin. The device will
continue to latch data into the registers until a stop
condition is detected. The device generates an
acknowledge after each byte of data written.
Read Operation:
When the read/write bit (LSB) is
HIGH and a valid address is decoded, the device will
transmit the data from the internal register on the
following eight
SCLK
cycles. Following the transfer of
the register data and the acknowledge from the master,
the device will release the data bus.
Reset:
At power-up the serial port defaults to the states
indicated in boldface type. The device also responds to
the system level reset that is transmitted through the
serial port. When the master sends the address
00000000 followed by the data 00000110, the device
resets to the default condition.
Rev 1.0
Following a 3:1 input mux stage is a unity-gain FB
video driver. The FB video driver is designed to
match the video drivers of RGB in bandwidth and
time delay and can support a minimum load of
300Ω.
Chip Power Down
The whole chip (except negligible on-chip biasing
circuit) can be powered down by setting Pdwn pin to
high (5V).
Configurable Device Address
Dev_Addr pin sets the address of the 5303B device.
There are two possible device addresses that the
5303B can have:
Device Address
1001000x
1010000x
Description
Dev_Addr pin left OPEN (Default)
Dev_Addr pin connected to GND
In the case of picture-in-picture or 6-channel inputs
application, a second device is required to have a
different address from the first or original device.
This can be done by connecting the Dev_Addr pin of
the second device to GND while leaving the
Dev_Addr pin of the first device OPEN or
unconnected.
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©
2005 TERIDIAN Semiconductor Corporation
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
