FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Appendix B: Revision History
Revision
1.0
Date
February 27,
2009
Description
Initial release. Changes with respect to PDS v1.3:
1) Corrected Timer/Counter 0/1 label in Table 22.
2) Corrected entries for DIO29 and DIO43 in Table 39.
3) Updated unused/reserved bits in I/O RAM tables, added descrip-
tion for
WE
register.
4) Documented blink capability for both SEG18 and SEG19.
5) Changed package for 71M6532D/F to LQFP-100, updated all pin
tables and I/O RAM tables accordingly.
6) Replaced graph showing system performance specification over
temperature with specification on accuracy of VREF compensa-
tion.
7) Added explanation for hysteresis at the V1 pin in Applications
Section.
8) Added note on recommended bypass capacitors C1 and C2 in
Electrical Specification.
9) Removed access to I/O RAM from SPI Port description.
10) Updated numerous parameters in Electrical Specification (tem-
perature sensor, supply current for mission and battery modes).
11) Corrected number of pre-boot cycles in Flash Memory Section.
12) Updated entries in I/O RAM table under “Wake” column.
Updated mechanical drawing for QFN-68 package.
Replaced Figure 19 with single-phase example.
Corrected LQFP-100 package drawing (Figure 50).
Applied minor corrections and enhancements to diagrams.
Updated number range for
RTC_ADJ
to 0 – 0x7F and tolerance for ex-
posed pad in Figure 46 to 0.1 mm. Corrected bit range for
CE_LCTN
to
[7:0]
and functional description for
TMOD[7]
and
TMOD[3]
in Table
22. Added maximum value for
WRATE
and text stating that registers
RTC_SEC
to
RTC_YR
do not change at reset. Added V LSB entry for
sag detection in CE Interface Description, text regarding hysteresis at
section 3.10, note that VX pin is not supported by standard CE code,
and description of
STOP
and
IDLE
bits in
PCON
register. Changed
value for Wh accuracy percentage on title page (value stated for
room temperature).
1.1
July 27, 2009
1.2
October 21, 2009
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