Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4
4.1
Firmware Interface
I/O RAM and SFR Map – Functional Order
Unused bits are labeled as “Not Used” and grayed out. These bits contain no memory and are read by the MPU as zero. Bits labeled as “Re-
served” may be in use and should not be changed from the values given in parentheses. This table lists only the SFR registers that are not ge-
neric 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with ‡ apply to the 71M6532D/F only and should be 0 for
the other device.
Table 48: I/O RAM Map in Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
EQU[2:0]
CE_E
CE10MHZ
Not Used
2000
CE1
PRE_SAMPS[1:0]
SUM_CYCLES[5:0]
2001
CE2
CHOP_E[1:0]
RTM_E
WD_OVF
EX_RTC
EX_XFR
Not Used
2002
COMP0
PLL_OK
COMP_STAT
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
2003
CONFIG0
VREF_CAL
PLS_INV
CKOUT_E
VREF_DIS
MPU_DIV[2:0]
Not Used
2004
CONFIG1
ECK_DIS
M26MHZ
ADC_E
MUX_ALT
M40MHZ
Not Used
Not Used
Not Used
2005
VERSION
VERSION[7:0]
2006
CONFIG2
OPT_TXE[1:0]
EX_PLL
EX_FWCOL
FIR_LEN[1:0]
OPT_FDC[1:0]
2007
CE3
MUX_DIV[3:0]
Not Used
209D
CE4
BOOT_SIZE[7:0]
20A7
CE5
CE_LCTN[7:0]
20A8
WAKE
WAKE_ARM
SLEEP
LCD_ONLY
WAKE_RES
WAKE_PRD[2:0]
Not Used
20A9
TMUX
TMUX[4:0]
Not Used
20AA
ANACTRL
LCD_DAC[2:0]
CHOP_I_EN‡
Reserved (0000)
20AB
CONFIG3
SEL_IBN‡
CHOP_IB‡
SEL_IAN‡
CHOP_IA‡
20AC
Not Used
Not Used
CONFIG4
Reserved (0) Reserved (0)
Not Used
Reserved (0) Reserved (0)
20AD
Not Used
Interrupts and WD Timer:
INTBITS
WD_RST
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SFR F8
IFLAGS
IE_WAKE
IE_PB
IE_FWCOL1 IE_FWCOL0
IE_RTC
IE_XFER
SFR E8
IE_PLLFALL IE_PLLRISE
Flash Memory:
ERASE
FLSH_ERASE[7:0]
SFR 94
FLSHCTL
SFR B2
PREBOOT
SECURE
WRPROT_BT WRPROT_CE
FLSH_MEEN
FLSH_PWE
Not Used
FL_BANK
SFR B6
FLBANK[2:0]
Not Used
PGADR
FLSH_PGADR[5:0]
Not Used
SFR B7
70
© 2005-2009 TERIDIAN Semiconductor Corporation
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