FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5.4
5.4.1
Performance Specifications
Input Logic Levels
Table 64: Input Logic Levels
Condition
Min
2
Typ
Max
0.8
VIN=0 V, ICE_E=1
10
10
-1
VIN = V3P3D
10
10
-1
-1
100
100
1
1
µA
µA
µA
µA
100
100
1
µA
µA
µA
Unit
V
V
Parameter
Digital high-level input voltage
a
, V
IH
Digital low-level input voltage
a
, V
IL
Input pull-up current, I
IL
E_RXTX,
E_RST, CKTEST
Other digital inputs
Input pull down current, I
IH
ICE_E
RESET
PB
Other digital inputs
a
0
0
0
In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.
5.4.2
Output Logic Levels
Table 65: Output Logic Levels
Condition
I
LOAD
= 1 mA
I
LOAD
= 15 mA
I
LOAD
= 1 mA
I
LOAD
= 15 mA
I
SOURCE
=1 mA
I
SINK
=20 mA
Min
V3P3D–0.4
V3P3D-0.6
0
Typ
Max
Unit
V
V
V
V
V
V
Parameter
Digital high-level output voltage V
OH
Digital low-level output voltage V
OL
OPT_TX V
OH
(V3P3D-OPT_TX)
OPT_TX V
OL
0.4
0.8
0.4
0.7
5.4.3
Power-Fault Comparator
Table 66: Power-Fault Comparator Performance Specifications
Condition
Vin = VBIAS – 100 mV
+100 mV overdrive
Voltage at V1 rising
Voltage at V1 falling
Min
-20
0.8
Typ
Max
+15
1.2
100
100
-10
Unit
mV
μA
µs
μs
mV
Parameter
Offset Voltage: V1-VBIAS
Hysteresis Current: V1
Response Time: V1
WDT Disable Threshold: V1-V3P3A
10
-400
8
37
5.4.4
Battery Monitor
Table 67: Battery Monitor Performance Specifications (BME= 1)
Condition
[M40MHZ,
M26MHZ]
= [00], [10], or [11]
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
FIR_LEN=0
FIR_LEN=1
FIR_LEN=2
(L=138)
(L=288)
(L=384)
(L=186)
(L=384)
(L=588)
Min
27
(-10%)
Typ
45
-48.7
-5.35
-2.26
-19.8
-2.26
-0.63
0
Parameter
Load Resistor
Max
63
(+10%)
LSB Value
[M40MHZ,
M26MHZ]
= [01]
(-10%)
(+10%)
Offset Error
-200
+100
Unit
kΩ
μV
μV
μV
μV
μV
μV
mV
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
97
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
