FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
5.9.3
Digital Pins
Table 86: Digital Pins
Type Circuit
Description
O
5
LCD Common Outputs: These 4 pins provide the select signals for
the LCD display.
Dedicated LCD Segment Output pins.
O
5
1, 4, 5 Multi-use pins, configurable as either emulator port pins (when ICE_E
1, 4, 5 pulled high) or LCD SEG drivers (when ICE_E tied to GND).
4, 5
ICE enable. When zero, E_RST, E_TCLK and E_RXTX become
2
SEG32, SEG33 and SEG38 respectively. For production units, this
pin should be pulled to GND to disable the emulator port.
CKTEST/SEG19,
O
4, 5
Multi-use pins, configurable as either multiplexer/clock output or LCD
MUXSYNC/SEG7
segment driver using the I/O RAM registers
CKOUT_E
or
MUX_SYNC_E.
Digital output test multiplexer. Controlled by
TMUX[3:0].
TMUXOUT
O
4
OPT_RX/DIO1
I/O
3, 4, 7 Multi-use pin, configurable as Optical Receive Input or general DIO.
When configured as OPT_RX, this pin receives a signal from an external
photo-detector used in an IR serial interface.
If this pin is unused it
must be configured as an output or terminated to V3P3D or GNDD.
Multi-use pin, configurable as either optical LED transmit output,
OPT_TX/DIO2
I/O
3, 4
WPULSE, RPULSE, or general DIO. When configured as OPT_TX,
this pin is capable of directly driving an LED for transmitting data in
an IR serial interface.
Chip reset: This input pin is used to reset the chip into a known state.
RESET
I
2
For normal operation, this pin is pulled low. To reset the chip, this pin
should be pulled high. This pin has an internal 30 μA (nominal) cur-
rent source pull-down. No external reset circuitry is necessary.
UART input.
If this pin is unused it must be configured as an
RX
I
3
output or terminated to V3P3D or GNDD.
UART output.
TX
O
4
TEST
I
7
Enables Production Test.
This pin must be grounded in normal
operation.
Push button input. This pin must be at GNDD when not active. A
PB
I
3
rising edge sets the
IE_PB
flag. It also causes the part to wake up if it
is in SLEEP or LCD mode. PB does not have an internal pull-up or
pull-down.
1)
Not all pins available on the 71M6531D/F or 71M6532D/F.
Pin types: P = Power, O = Output, I = Input, I/O = Input/Output.
The circuit number denotes the equivalent circuit, as specified in Section 5.9.4. I/O Equivalent Circuits.
I/O
I/O
O
I
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
111
Name
COM3,COM2,
COM1,COM0
SEG0…SEG2,
SEG7, SEG8
SEG12…SEG18
SEG20…SEG23
SEG24/DIO4…
SEG35/DIO15,
SEG37/DIO17,
SEG48/DIO28,
SEG49/DIO29,
SEG63/DIO43…
SEG66/DIO46
SEG3/PCLK
SEG4/PSDO
SEG5/PCSZ
SEG6/PSDI
E_RXTX/SEG9
E_RST/SEG11
E_TCLK/SEG10
ICE_E
O
I/O
Dedicated LCD Segment Output pins (71M6532D/F only).
5
3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or DIO.
(DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface;
WPULSE = DIO6, VARPULSE = DIO7 when configured as pulse
outputs).
Unused pins must be configured as outputs or termi-
nated to V3P3/GNDD.
1)
I/O
3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or SPI PORT.
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