71M6533/71M6534 Data Sheet
FDS_6533_6534_004
5.4 Performance Specifications
5.4.1 Input Logic Levels
Table 65: Input Logic Levels
Parameter
Condition
Min
Typ
Max
Unit
V
Digital high-level input voltagea, VIH
Digital low-level input voltagea, VIL
2
0.8
V
Input pull-up current, IIL
E_RXTX, E_ISYNC
E_RST, CKTEST
VIN=0 V, ICE_E=1
100
100
1
µA
µA
µA
10
10
-1
Other digital inputs
0
Input pull down current, IIH
VIN = V3P3D
ICE_E
RESET
PB
10
10
-1
100
100
1
µA
µA
µA
µA
0
0
Other digital inputs
-1
1
a In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.
5.4.2 Output Logic Levels
Table 66: Output Logic Levels
Parameter
Condition
Min
V3P3D–0.4
V3P3D-0.6
0
Typ
Max
Unit
V
Digital high-level output voltage VOH ILOAD = 1 mA
ILOAD = 15 mA
V
Digital low-level output voltage VOL
ILOAD = 1 mA
ILOAD = 15 mA
ISOURCE=1 mA
ISINK=20 mA
0.4
0.8
0.4
0.7
V
V
OPT_TX VOH (V3P3D-OPT_TX)
OPT_TX VOL
V
V
5.4.3 Power-Fault Comparator
Table 67: Power-fault Comparator Performance Specifications
Parameter
Offset Voltage: V1-VBIAS
Hysteresis Current: V1
Condition
Min
-20
0.8
Typ
Max
Unit
mV
μA
+15
1.2
Vin = VBIAS – 100 mV
+100 mV overdrive
Response Time: V1
10
37
100
-10
μs
WDT Disable Threshold: V1-V3P3A
-400
mV
5.4.4 V2 Comparator (71M6534 only)
Table 68: V2 Comparator Performance Specifications
Parameter
Offset Voltage: V2-VBIAS
Hysteresis Current
Condition
Min
-20
0.8
Typ
Max
+15
1.2
1
Unit
mV
μA
Vin = VBIAS – 100 mV
+100 mV overdrive
Response Time
μs
104
© 2007-2009 TERIDIAN Semiconductor Corporation
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