FDS_6533_6534_004
EECTRL Byte Written
Write -- No HiZ
SCLK (output)
SDATA (output)
SDATA output Z
BUSY
(bit)
D7
(LoZ)
71M6533/71M6534 Data Sheet
INT5 not issued
CNT Cycles (0 shown)
EECTRL Byte Written
Write -- HiZ
SCLK (output)
SDATA (output)
SDATA output Z
BUSY
(bit)
(HiZ)
INT5 not issued
CNT Cycles (0 shown)
Figure 13: 3-Wire Interface. Write Command when CNT=0
EECTRL Byte Written
CNT Cycles (6 shown)
Write -- With HiZ and WFR
SCLK (output)
SDATA (out/in)
SDATA output Z
BUSY
(bit)
D7
D6
D5
(From 6520)
From 653X
(LoZ)
D4
D3
D2
BUSY
(From EEPROM)
(HiZ)
READY
INT5
Figure 14: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
1.4.11 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
locations. It is also able to send commands to the MPU. The interface to the slave port consists of the
PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3
to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the
SPE
bit in I/O RAM.
Access to I/O RAM (Configuration RAM) should not be attempted via the SPI Port.
A typical SPI transaction is as follows: While PCSZ is high, the port is held in an initialized/reset state.
During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When
PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. A transaction consists of
an 8-bit command, a 16-bit address, and then one or more bytes of data. The transaction ends when
PCSZ is raised. Some transactions may consist of a command only.
The last issued SPI command and address (if part of the command) are available to the MPU in registers
SP_CMD
and
SP_ADDR.
The SPI port supports data transfers at 1 Mb/s in mission mode, and 16 kb/s in brownout mode.
illustrates the read and write timing of the SPI Interface. The SPI commands are described in
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
49
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
