71M6533/71M6534 Data Sheet
FDS_6533_6534_004
readies the timer to start when the processor writes to the SLEEP or LCD_ONLY registers. The timer is
reset and disarmed whenever the processor is awake. Thus, if it is desired to wake the MPU periodically
(every 5 seconds, for example) the timer must be rearmed every time the part returns from SLEEP or
LCD mode.
2.6 Data Flow
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 28. In a typical appli-
cation, the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and
VB, performing calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h for four-
quadrant metering. These measurements are then accessed by the MPU, processed further and output
using the peripheral devices available to the MPU. Figure 28 illustrates the CE/MPU data flow.
Pulses
IRQ
Processed
Metering
Data
CE
MPU
Data
Samples
Pre-
Processor
Post-
Processor
I/O RAM (Configuration RAM)
Figure 28: MPU/CE Data Flow
2.7 CE/MPU Communication
Figure 29 shows the functional relationships between the CE and the MPU. The CE is controlled by the
MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively pro-
cessing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is
updating data to the output region of the RAM. This will occur whenever the CE has finished generating a
sum by completing an accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples. Inter-
rupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section 4.3 CE Interface Description for additional information on setting up the device using the
MPU firmware.
VAR
(DIO7)
PULSES
W (DIO6)
DISPLAY (Memory
mapped LCD
segments)
APULSEW
APULSER
EXT PULSE
SERIAL
(UART0/1)
SAG CONTROL
MPU
EEPROM
(I2C)
SAMPLES
ADC
DATA
CE BUSY
CE
DIO
XFER BUSY
INTERRUPTS
Mux Control
I/O RAM (Configuration RAM)
Figure 29: MPU/CE Communication
64
© 2007-2009 TERIDIAN Semiconductor Corporation
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