73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
FUNCTIONAL DESCRIPTION
HYBRID AND RELAY DRIVER
To make designs more cost effective and space
efficient, the 73K324BL includes the 2-wire to 4-wire
hybrid with sufficient drive to interface directly to the
telecom coupling transformers. In addition, an off
hook relay driver with 40 mA drive capability is also
included to allow use of commonly available
mechanical telecom relays.
QAM MODULATOR/DEMODULATOR
The 73K324BL encodes incoming data into quad-bits
represented by 16 possible signal points with specific
phase and amplitude levels. The base-band signal is
then filtered to reduce intersymbol interference on the
band limited telephone network. The modulator
transmits this encoded data using either a 1200 Hz
(originate mode) or 2400 Hz (answer mode) carrier.
The demodulator, although more complex, essentially
reverses this procedure while also recovering the
data clock from the incoming signal. Adaptive
equalization corrects for varying line conditions by
automatically
changing
filter
parameters
to
compensate for line characteristics.
DPSK MODULATOR/DEMODULATOR
The 73K324BL modulates a serial bit stream into
di-bit pairs that are represented by four possible
phase shifts as prescribed by the Bell 212A/V.22
standards. The base-band signal is then filtered to
reduce intersymbol interference on the bandlimited 2-
wire PSTN line. Transmission occurs on either a 1200
Hz (originate mode) or 2400 Hz carrier (answer
mode).
Demodulation is the reverse of the
modulation process, with the incoming analog signal
eventually decoded into di-bits and converted back to
a serial bit stream. The demodulator also recovers
the clock, which was encoded into the analog signal
during modulation. Demodulation occurs using either
a 1200 Hz carrier (answer mode or ALB originate
mode) or a 2400 Hz carrier (originate mode or ALB
answer mode). The 73K324BL use a phase locked
loop coherent demodulation technique that offers
excellent performance. Adaptive equalization is also
used in DPSK modes for optimum operation with
varying line conditions.
FSK MODULATOR/DEMODULATOR
The FSK modulator produces a frequency modulated
analog output signal using two discrete frequencies to
represent the binary data. V.21 mode uses 980 and
1180 Hz (originate, mark and space) or 1650 and
1850 Hz (answer, mark and space) are used in V.21
mode. V.23 mode uses 1300 and 2100 Hz for the
main channel and 390 and 450 Hz for the back
channel. Demodulation involves detecting the
received frequencies and decoding them into the
appropriate binary value. The rate converter and
scrambler/descrambler are automatically bypassed in
the FSK modes.
PASSBAND FILTERS AND EQUALIZERS
High and low band filters are included to shape the
amplitude and phase response of the transmit and
receive signals and provide compromise delay
equalization and rejection of out-of-band signals.
Amplitude and phase equalization are necessary to
compensate for distortion of the transmission line and
to reduce intersymbol interference in the band limited
receive signal. The transmit signal filtering
corresponds to a 75% square root of raised Cosine
frequency response characteristic.
ASYNCHRONOUS MODE
The asynchronous mode is used for communication
with asynchronous terminals which may communicate
at 600,1200, or 2400 bps +1%, -2.5% even though
the modem’s output is limited to the nominal bit rate
±.01% in DPSK and QAM modes. When transmitting
in this mode the serial data on the TXD input is
passed through a rate converter which inserts or
deletes stop bits in the serial bit stream in order to
output a signal that is the nominal bit rate ±.01%. This
signal is then routed to a data scrambler and into the
analog modulator where quad-bit/di-bit encoding
results in the output signal. Both the rate converter
and scrambler can be bypassed for handshaking, and
synchronous operation as selected. Received data is
processed in a similar fashion except that the rate
converter now acts to reinsert any deleted stop bits
and output data to the terminal at no greater than the
bit rate plus 1%. An incoming break signal (low
through two characters) will be passed through
without incorrectly inserting a stop bit.
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©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
