73M1903C
Modem Analog Front End
DATA SHEET
CONTROL REGISTER MAP
The following Table 2 shows the map of addressable registers in the 73M1903C. Each register and its
bits are described in detail in the following sections.
Register
Name
CTRL
TEST
DATA
DIR
Register04
Register05
REV
Register07
PLL_PSEQ
PLL_RST
PLL_KVCO
PLL_DIV
PLL_SEQ
XTAL_BIAS
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
Default
08h
00h
FFh
FFh
00h
00h
60h
00h
00h
0Ah
22h
12h
00h
C0h
BIT 7
ENFE
TMEN
GPIO7
DIR7
BIT 6
SELTX2
DIGLB
GPIO 6
DIR6
BIT 5
BIT 4
BIT 3
TXDIS
CkoutEn
GPIO 3
DIR3
BIT 2
BIT 1
BIT 0
RXGAIN
HC
GPIO 0
DIR0
TXBST(1:0)
ANALB
GPIO 5
DIR5
INTLB
GPIO 4
DIR4
RXG(1:0)
RXPULL
GPIO 2
DIR2
SPOS
GPIO 1
DIR1
Reserved
Reserved
Rev(3:0)
FSDEn
Reserved
Pseq(7:0)
Prst(2:0)
Ichp(3:0)
-
Xtal(1:0)
Reserved
Reserved
Ndvsr(6:0)
Nseq(7:0)
-
Nrst(2:0)
Pdvsr(4:0)
Kvco(2:0)
Reserved
PLL_LOCK
0Eh
00H
Frcvco PwdnPll
LockDet
-
-
-
-
-
Note: Register or bit names in bold underline denotes the READ ONLY bits and registers.
Register bits marked “-“ are not used. Writing any value to these bits won’t affect the operation.
Reserved are bits reserved for factory test purpose only. Do not attempt to write these locations to values
other than their default to prevent unexpected operation.
Register Bit notations used in this document are as follows.
- Registerxx: Register05 represents the register with Address 0x05
- BIT(s)NAME(MSB:LSB) ; Rev(3:0) represents 4 bits of Rev3, Rev2, Rev1 and Rev0.
-(RegisterAddress[BIT(s)]) ; (0X00[7]) represents Bit 7 of Register address 0x00, ENFE bit
(0X06[7:4]) represents Bit 7, Bit 6, Bit 5 and Bit4 of Register address 06, Rev(3:0).
Table 2: Register Map
Page: 11 of 46
©
2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
