73M1903 Data Sheet
DS_1903_032
5.4 Control Register (CTRL2): Address 01h
Reset State 00h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMEN
DIGLB
ANALB
INTLB
CkoutEn RXPULL SPOS
HC
TMEN
DIGLB
1 = Enable test modes.
1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter
input. DIGITAL LOOPBACK
ANALB
INTLB
1 = Tie the analog output of the transmitter to the analog input of the receiver. ANALOG
LOOPBACK
1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter
input. INTERNAL LOOPBACK
CkoutEn
RXPULL
1 = Enable the CLKOUT output; 0 = CLKOUT tri-stated. For test purposes only; do not use
in normal operation.
1 = Pulls DC Bias to RXAP/RXAN pins, through 100 kΩ each, to VREF, to be used in testing
Rx path.
0 = No DC Bias to RXAP/RXAN pins.
SPOS
HC
1 = Control frames occur after one quarter of the time between data frames has elapsed.
0 = Control frames occur half way between data frames.
1 = FS is under hardware control, bit 0 of data frames on SDIN is bit 0 of the transmit word
and control frames happen automatically after every data frame.
0 = FS is under software control, bit 0 of data frames on SDIN is a control frame request bit
and control frames happen only on request.
5.5 Revision Register: Address 06h
Reset State 30h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev3
Rev2
Rev1
Rev0
Unused
Reserved Reserved Reserved
Bits 7-4 contain the revision level of the 73M1903 device. The rest of this register is for chip development
purposes only and is not intended for customer use. Do not write to shaded locations.
24
Rev. 2.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
