DS_6612_001
Interrupt Priority 0 Register (IP0)
Table 33: The
IP0
Register
MSB
–
WDTS
IP0[5]
IP0[4]
IP0[3]
IP0[2]
IP0[1]
78M6612 Data Sheet
LSB
IP0[0]
Note: WDTS is not used for interrupt controls.
Interrupt Priority 1 Register (IP1)
Table 34: The
IP1
Register
MSB
–
–
IP1[5]
IP1[4]
IP1[3]
IP1[2]
IP1[1]
LSB
IP1[0]
Table 35: Priority Levels
IP1[x]
0
0
1
1
IP0[x]
0
1
0
1
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
Table 36: Interrupt Polling Sequence
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
External interrupt 2
External interrupt 1
External interrupt 3
Timer 1 interrupt
External interrupt 4
Serial channel 0 interrupt
External interrupt 5
External interrupt 6
Polling sequence
Rev. 1.2
37
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
