78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
LINE BUILD-OUT
The Line Build-Out (LBO) function controls the
transmit amplitude and pulse shape in DS3 and
STS-1 modes. The selection of LBO depends on
the amount of cable the transmitter is connected to.
When less than 225 ft of cable is used, the
corresponding LBOx pin or LBO bit should be high.
When 225ft or more cable is used the corresponding
LBO setting (LBOx pin or LBO bit) should be low.
LBO can be controlled either from pins or from
register settings, depending on the status of the
Register Control bit, REGEN.
TRANSMIT ENABLE
The TXEN bit in the Mode Control Register controls
the transmitter output.
When logic zero, the
transmitter output is disabled. This feature is used to
disable ports as well as to multiplex two or more
transceivers to one port. The transmitter of any port
can also be disabled by floating the respective LBOx
pin, in which case it will also power-down the entire
transmitter.
See section on the Power-Down
Function for more info.
TRANSMIT MONITOR
The transmit monitor function detects activity on the
transmitter output at the LOUTPx and LOUTNx pins.
When there is a transmitter fault, in the case of an
open or short on the chip, the transformer, or the
circuit board, the transmit signal amplitude will be
altered. The transmit monitor detects the amplitude
of the driven signal. The TXNW signal (bit) goes
high when the amplitude of the transmit signal is
outside a valid amplitude range. When the signal
amplitude is either too high or too low for longer than
a specified duration, the TXNW bit goes high (See
Transmit Monitor Specifications, pg.28). The TXNW
signal can be also used to trigger an interrupt on the
INTRx pin when serial interface control is not
available.
JITTER ATTENUATOR
Jitter Attenuation function is provided on-chip. The
Jitter Attenuator can be configured to be in the
transmit or the receive path. When configured in the
transmit path, the input clock at TCLK pin is passed
through a very low bandwidth digital PLL. The
corresponding transmit data is buffered into a FIFO
and clocked out using the de-jittered output clock of
the PLL. When configured in the receive path, the
recovered clock is passed through the low
bandwidth digital PLL, and the corresponding
receive data is buffered into the FIFO and clocked
out using the de-jittered clock.
When serial interface control is not available, the
MSL1 pin is provided for global Jitter Attenuator
mode selection. Upon power-up or reset, the state
of the MSL1 pin is sensed and mapped into the
JAEN and JASL register bits for all channels,
representing the appropriate mode of operation.
After power-up or reset, the state of the MSL1 pin is
ignored. The state of the MSL1 pin, and the
corresponding Jitter Attenuator configuration is
shown below.
MSL1 pin
L
H
Z
PLL Bandwidth
A PLL response with effectively one pole below 27
Hz is adequate to meet the ETSI TBR24 E3
standards. A PLL response with one pole below 40
Hz is adequate to meet the GR-499 (Cat I) DS3
standards. One of two bandwidths can be selected
via register settings.
The PLL bandwidth is
proportional to the data rate as follows:
Line Rate
E3
DS3
STS1
JABW bit
0
1
0
1
0
1
PLL Bandwidth
(Hz)
*13
188
*17
245
20
*283
Jitter Attenuator Mode
Jitter Attenuator in receive path
Jitter Attenuator in transmit path
Jitter Attenuator disabled
The Jitter Attenuator can be configured
independently for each channel by writing to the
Jitter Attenuator Control Register (JACR) as follows:
JAEN
bit
0
1
1
JASL
bit
X
0
1
Jitter Attenuator Mode
Jitter Attenuator disabled
Jitter Attenuator configured
to be in the receive path
Jitter Attenuator configured
to be in the transmit path
*The default state of the JABW bit depends on
which line-rate is selected through the MSL0 pin. If
E3 or DS3 mode is selected, the default state is ‘0’.
If STS1 mode is selected, the default state is ‘1’.
Rev 2.2
Page 5 of 36
2005 Teridian Semiconductor Corporation
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
