78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION
(continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the interrupt pins to be activated. User may set as many bits as
required.
BIT
NAME
TYPE
DFLT
VALUE
0
DESCRIPTION
Interrupt Pin Polarity Selection:
7
INPOL
R/W
0 : Interrupt output is active-low (default)
1 : Interrupt output is active-high
6:2
--
R/W
01000
Reserved for future use
TXLOL Error Mask
(active low):
Gates the TXLOL register bit to the INTTXB interrupt pin.
0: Mask
1: Pass
FIERR Error Mask
(active low):
Gates the respective FIERR register bit to the INTTXB interrupt pin.
0: Mask
1: Pass
1
MTLOL
R/W
1
0
MFERR
R/W
1
ADDRESS 0-2: I/O CONTROL REGISTER
BIT
7:1
NAME
--
TYPE
R/W
DFLT
VALUE
XXXXXXX
DESCRIPTION
Unused
Redundant Channel Enable:
Enables transmit monitor outputs at CMI2P/N pins.
0: Disable
1: Enable
0
RCSL
R/W
0
Page: 12 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
