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THC63LVDM83E 参数 Datasheet PDF下载

THC63LVDM83E图片预览
型号: THC63LVDM83E
PDF下载: 下载PDF文件 查看货源
内容描述: 小型/ 24Bit的彩色LVDS发送器 [SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER]
分类和应用:
文件页数/大小: 13 页 / 333 K
品牌: THINE [ THINE ELECTRONICS, INC. ]
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THC63LVDM83E_Rev.1.30_E
THC63LVDM83E
SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER
General Description
The THC63LVDM83E transmitter is designed to
support pixel data transmission between Host and
Flat Panel Display up to 1080p/WUXGA resolutions.
The THC63LVDM83E converts 28bits of
CMOS/TTL data into LVDS (Low Voltage
Differential Signaling) data stream. The transmitter
can be programmed for rising edge or falling edge
clocks through a dedicated pin. At a transmit clock
frequency of 160MHz, 24bits of RGB data and 4bits
of timing and control data (HSYNC, VSYNC, DE,
CONT1) are transmitted at an effective rate of
1120Mbps per LVDS channel.
Features
½49pin
0.65mm pitch VFBGA Package
½Wide
dot clock range: 8-160MHz suited for
TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)
PC Signal : QVGA(8MHz) - WUXGA(154MHz)
½1.2V
to 3.3V CMOS inputs are supported.
½LVDS
swing is reducible by RS-pin to reduce EMI
and power consumption.
½PLL
requires no external components.
½On
chip jitter filtering.
½Spread
Spectrum Clock input tolerant.
½Power
down mode.
½Input
clock triggering edge is selectable by R/F-pin.
½Operates
from a Single 3.3V Supply and
110mW(typ.) at 75MHz.
Block Diagram
CMOS/TTL
INPUTS
TA0-6
TB0-6
TC0-6
TD0-6
7
7
7
7
THC63LVDM83E
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
TD +/-
(56-1120Mbit/On Each
LVDS Channel)
PLL
TCLK +/-
CLOCK
(LVDS)
8-160MHz
TRANSMITTER
CLKIN
(8 to 160MHz)
R/F
/PDWN
RS
Copyright©2012 THine Electronics, Inc.
CMOS/TTL PARALLEL
TO SERIAL
1
THine Electronics, Inc.