THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions.
The THC63LVD823 converts 48bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
In Single Link, the transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, the transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
•
Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
•
PLL requires No external components
•
Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
•
Supports Single Link, Dual-in (TTL)/Single-out
•
•
•
•
•
•
•
(LVDS) pixel up to 135MHz dot clock for SXGA+
Supports Single Link, Single-in (TTL)/Single-out
(LVDS) pixel up to 85MHz dot clock for XGA
Clock edge selectable
Supports Reduced swing LVDS for Low EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT
8
MUX
8
8
8
8
8
PARALLEL TO SERIAL
LVDS OUTPUT
RED1
1st DATA
GREEN1
BLUE1
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TCLK1 +/-
(25 to 135MHz)
1st Link
HSYNC
VSYNC
DE
TA2 +/-
PARALLEL TO SERIAL
8
8
8
TB2 +/-
TC2 +/-
TD2 +/-
TCLK2 +/-
(25 to 85MHz)
2nd Link
RED2
2nd DATA
GREEN2
BLUE2
TRANSMITTER CLOCK IN
(25 to 85MHz)
R/F
/PDWN
PLL
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
