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Circuit Description
2.2.4
Analog Inputs
The EVM provides eight analog inputs, using an SMA connector for each of the eight channels of the
ADC. SMA channel inputs are J9, J10, J13, J14, J17, J18, J21, and J22. By default, the ADC accepts a
single-ended input and translates it to a differential signal using a Mini Circuits TC1-1T transformer. The
ADC inputs are dc-biased by feeding the ADC VCM voltage to the transformer center tap on the
secondary windings. Provisions have also been made on the EVM to allow for differential inputs using two
SMAs per input channel.
2.2.5
Digital Outputs
The serial LVDS digital outputs can be accessed through the J8 output connector. The EVM is designed
to be interfaced to the TI TSW1200 Rev B deserializer card, which plugs into J8. In addition, the EVM can
be interfaced to the ADSDeSer-50EVM using a translation card, the ADS5281DeSerAdapter. Both the
TSW1200 Rev B and the ADSDeSer-50EVM contain the required parallel 100-Ω termination resistor that
must be placed at the receiver to terminate each LVDS data pair properly.
Note:
TSW1200 Rev B:
Users wishing to use the TSW1200 for deserialization should note that the
minimium ADC sampling frequency this can be operated at is 32 MHz. The TSW1200 uses a
digital clock manager (DCM) with a minimium operational frequency of 32 MHz.
Full documentation on the TI ADSDeSer-50EVM deserializer is found in the
ADSDeSer-50EVM Evaluation
Module User's Guide
Connecting Xilinx FPGAs to Texas Instruments ADS527x Series
ADCs,
Xilinx™ application report
The VHDL deserializer source code can be found on the
Xilinx Web site.
SLAU205 – January 2008
9
TI [ TEXAS INSTRUMENTS ]
