TIMING DIAGRAMS
CS
t
3
SCLK
(POL = 0)
SCLK
(POL = 1)
t
4
D
IN
MSB
t
5
LSB
t
7
MSB
(1)
t
8
LSB
(1)
t
9
t
6
t
2
t
11
t
1
t
2
t
10
(Command or Command and Data)
D
OUT
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
ADS1240 or ADS1241
Resets On
Falling Edge
300 • t
OSC
< t
12
< 500 • t
OSC
t
13
t
13
t
13
: > 5 • t
OSC
550 • t
OSC
< t
14
< 750 • t
OSC
t
12
t
14
t
15
1050 • t
OSC
< t
15
< 1250 • t
OSC
SCLK
DIAGRAM 1.
t
DATA
DRDY
t
17
SCLK
t
19
t
18
RESET, DSYNC, PDWN
t
16
DIAGRAM 2.
TIMING CHARACTERISTICS TABLES
SPEC
t
1
t
2
t
3
t
4
t
5
t
6
t
7(1)
t
8(1)
t
9
t
10
t
11
DESCRIPTION
SCLK Period
SCLK Pulse Width, HIGH and LOW
CS low to first SCLK Edge; Setup
Time
(2)
D
IN
Valid to SCLK Edge; Setup Time
Valid D
IN
to SCLK Edge; Hold Time
Delay between last SCLK edge for D
IN
and first SCLK edge for D
OUT
:
RDATA, RDATAC, RREG, WREG
SCLK Edge to Valid New D
OUT
SCLK Edge to D
OUT
, Hold Time
Last SCLK Edge to D
OUT
Tri-State
NOTE: D
OUT
goes tri-state immediately when CS goes HIGH.
CS LOW time after final SCLK edge.
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (also SCLK Reset or RESET Pin)
Pulse Width
Allowed analog input change for next valid conversion.
DOR update, DOR data not valid.
First SCLK after DRDY goes LOW:
RDATAC Mode
Any other mode
0
ns
50
50
0
6
10
t
OSC
Periods
ns
ns
t
OSC
Periods
MIN
4
3
200
0
50
50
MAX
UNITS
t
OSC
Periods
DRDY Periods
ns
ns
ns
ns
t
16
t
17
t
18
t
19
4
2
4
16
4
5000
4
10
0
t
OSC
Periods
DRDY Periods
DRDY Periods
t
OSC
Periods
t
OSC
Periods
t
OSC
Periods
t
OSC
Periods
t
OSC
Periods
t
OSC
Periods
NOTES: (1) Load = 20pF 10kΩ to DGND.
(2) CS may be tied LOW.
6
ADS1240, 1241
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SBAS173C
TI [ TEXAS INSTRUMENTS ]
