CC3220
SWAS035A –SEPTEMBER 2016–REVISED FEBRUARY 2017
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Table 3-1. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
Select as
FUNCTION
PAD STATES
Dig.
Pin
Mux
Config.
Addl.
Analog
Mux
Muxed
With
JTAG
Pkg.
Pin
Dig. Pin Mux
Signal
Description
Signal
Direction
Pin Alias
Use
Wakeup
Source
Signal Name
LPDS(1)
Hib(2)
nRESET = 0
Config. Reg. Config.
Mode
Value
Digital DC-DC
input (connected to
chip input supply
[VBAT])
VIN_DCDC
_DIG
Supply
input
VIN_DCDC_
DIG
44
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
9
GPIO31
GPIO
I/O
I
UART0_RX
UART0 RX data
I2S audio port
frame sync
12
2
McAFSX
UART1_RX
McAXR0
O
I
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
User
config not
GPIO_PAD_
CONFIG_31
(0x4402 E11C)
UART1 RX data
DCDC_AN
A2_SW_P
45(9)
I/O
No
No
I2S audio port data
0 (RX/TX)
required
6
I/O
I/O
(8)
7
GSPI_CLK
General SPI clock
ANA2 DCDC
converter +ve
switching node
DCDC_ANA2_
SW_P
See (5)
N/A
DCDC_
ANA2_
SW_N
ANA2 DC-DC
converter -ve
switching node
Internal
power
DCDC_ANA2_
SW_N
46
47
48
49
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VDD_
ANA2
Internal
power
ANA2 DC-DC
output
VDD_ANA2
VDD_ANA1
VDD_RAM
Analog supply fed
by ANA2 DC-DC
output
VDD_
ANA1
Internal
power
Internal
power
VDD_RAM
SRAM LDO output
16
Terminal Configuration and Functions
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