OMAP-L138 Low-Power Applications Processor
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SPRS586A – JUNE 2009 – REVISED AUGUST 2009
1.4 Functional Block Diagram
JTAG Interface
System Control
Input
Clock(s)
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer (x3)
RTC/
32-kHz
OSC
ARM926EJ-S CPU
With MMU
4KB ETB
16KB
16KB
I-Cache D-Cache
8KB RAM
(Vector Table)
64KB ROM
C674x™
DSP CPU
AET
32KB
L1 Pgm
32KB
L1 RAM
ARM Subsystem
DSP Subsystem
Power/Sleep
Controller
Pin
Multiplexing
256KB L2 RAM
1024KB L2 ROM
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interfaces
Display
Video
Parallel Port Internal Memory Customizable Interface
EDMA3
(x2)
McASP
w/FIFO
McBSP
(x2)
I
2
C
(x2)
SPI
(x2)
UART
(x3)
LCD
Ctlr
VPIF
uPP
128KB
RAM
PRU Subsystem
Control Timers
Connectivity
External Memory Interfaces
ePWM
(x2)
eCAP
(x3)
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
EMAC
10/100 MDIO
(MII/RMII)
HPI
MMC/SD
(8b)
(x2)
SATA
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
DDR2/MDDR
Controller
(1)
Note: Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
OMAP-L138 Low-Power Applications Processor
7
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