SBAS451 – OCTOBER 2008..............................................................................................................................................................................................
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PIN CONFIGURATION
PW PACKAGE
TSSOP-24
(TOP VIEW)
LRCK
BCK
DIN
RST
SCKI
VDD
DGND
VCC1
VCOM
1
2
3
4
5
6
PCM1789
7
8
9
18 ZERO2/AMUTEO
17 AMUTEI
16 VCC2
15 AGND2
14 VOUTR
-
13 VOUTR+
24 ADR5/ADR1/RSV
23 MS/ADR0/RSV
22 MC/SCL/FMT
21 MD/SDA/DEMP
20 MODE
19 ZERO1
AGND1 10
VOUTL
-
11
VOUTL+ 12
TERMINAL FUNCTIONS
TERMINAL
NAME
LRCK
BCK
DIN
RST
SCKI
VDD
DGND
VCC1
VCOM
AGND1
VOUTL–
VOUTL+
VOUTR+
VOUTR–
AGND2
VCC2
AMUTEI
ZERO2/AMUTEO
ZERO1
MODE
MD/SDA/DEMP
MC/SCL/FMT
MS/ADR0/RSV
ADR5/ADR1/RSV
(1)
6
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I
I
I
I
I
—
—
—
—
—
O
O
O
O
—
—
I
O
O
I
I/O
I
I
I
PULL-
DOWN
Yes
Yes
No
Yes
No
—
—
—
—
—
No
No
No
No
—
—
No
No
No
No
No
No
Yes
No
5-V
TOLERANT
No
No
No
Yes
Yes
—
—
—
—
—
No
No
No
No
—
—
Yes
No
No
No
Yes
Yes
Yes
Yes
Audio data word clock input
Audio data bit clock input
Audio data input
Reset and power-down control input with active low
System clock input
Digital power supply, +3.3 V
Digital ground
Analog power supply 1, +5 V
Voltage common decoupling
Analog ground 1
Negative analog output from DAC left channel
Positive analog output from DAC left channel
Positive analog output from DAC right channel
Negative analog output from DAC right channel
Analog ground 2
Analog power supply 2, +5 V
Analog mute control input with active low
Zero detect flag output 2/Analog mute control output
(1)
with active low
Zero detect flag output 1
Control port mode selection. Tied to VDD: SPI, ADR6 = 1, pull-up: SPI,
ADR6 = 0, pull-down: H/W auto mode, tied to DGND: I
2
C
Input data for SPI, data for I
2
C
(1)
, de-emphasis control for hardware
control mode
Clock for SPI, clock for I
2
C, format select for hardware control mode
Chip Select for SPI, address select 0 for I
2
C, reserve (set low) for
hardware control mode
Address select 5 for SPI, address select 1 for I
2
C, reserve (set low) for
hardware control mode
DESCRIPTION
Open-drain configuration in out mode.
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