SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
High-Level
Pulse
VCC
50%
tw
Low-Level
Pulse
VCC
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
VCC
50%
tPLH
Reference
Input
tsu
Data
Input 50%
10%
90%
50%
th
90%
VCC
50%
10% 0 V
tf
Out-of-Phase
Output
VCC
0V
In-Phase
Output
50%
10%
tPHL
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
50%
0V
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Input
tr
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
