tm
TE
CH
T15L256A
SRAM
FEATURES
•
Access time: 35ns/70ns
•
Low power consumption : Active 200 mW(typ.)
•
Low operating current : 50mA
•
Single + 3.3V power supply
•
Fully static operation – No clock or refreshing
required
•
All inputs and outputs directly LVTTL compatible
•
Common I/O capability
•
Available packages : 28-pin 300 mil SOJ, 28-pin
SOP, TSOP-I (forward type ).
•
Output enable (
OE
) available for very fast access
32K X 8 LOW POWER
CMOS STATIC RAM
GENERAL DESCRIPTION
The T15L256A is a high speed, low power
CMOS static RAM organized as 32,768 x 8 bits that
operates on a single 3.3-volt power supply. This
device is packaged in standard 28-pin 300 mil SOJ ,
28-pin SOP, TSOP-I forward.
BLOCK DIAGRAM
Vcc
→
Vss
→
A0
→
A14
→
CS
→
OE
→
CONTROL
WE
→
←
I / O1
.
.
.
.
.
DECODER
CORE
ARRAY
PIN CONFIGURATION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
Vcc
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
DATA I/O
←
I / O8
SOJ
&
SOP
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CS
WE
OE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vcc
Vss
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable
Output Enable
Power Supply
Ground
PART NUMBER EXAMPLES
T15L256A-35J
T15L256A-70P
T15L256A-70D
PACKAGE
SOJ
TSOP-I
SOP
SPEED
35ns
70ns
70ns
TSOP-I
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: APR. 2001
Revision:C
TMT [ TAIWAN MEMORY TECHNOLOGY ]
