TE
tmCH
Preliminary T15M64A
PIN CONFIGURATION
N C
A 12
A 7
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V cc
W E
N C
N C
A 1 2
A 7
1
2
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
V cc
W E
N C
3
3
A 6
4
A 8
A 6
4
A 8
A 5
5
A 9
A 5
5
A 9
D IP
&
A 4
6
A 11
O E
A 4
6
A 1 1
O E
A 3
7
A 3
7
SO P
A 2
8
A 10
C S
A 2
8
A 1 0
C S
SO J
A 1
9
A 1
9
A 0
10
11
12
13
14
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
A 0
1 0
1 1
1 2
1 3
1 4
I/O 8
I/O 7
I/O 6
I/O 5
I/O 4
I/O 1
I/O 2
I/O 3
V ss
I/O 1
I/O 2
I/O 3
V ss
OE
A11
A9
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
2
3
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A8
4
NC
WE
VCC
NC
A12
A7
5
6
TSOP-I
7
8
9
10
11
12
13
14
A6
A5
A4
A1
A3
A2
PIN DESCRIPTION
SYMBOL
A0 - A12
DESCRIPTION
Address Inputs
I/O1 - I/O8
CS
Data Inputs/Outputs
Chip Select Inputs
Write Enable
WE
Output Enable
Power Supply
Ground
OE
Vcc
Vss
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: SEP. 2002
Revision:0.A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
