tm
TE
CH
T15N1024A
SRAM
FEATURES
•
Low-power consumption
- Active: 40mA at 55ns (Max.)
- CMOS Stand-by: 10uA (Max.)
•
55/70/100 ns access time
•
Equal access and cycle time
•
Single +2.4V to 3.6V Power Supply
•
TTL compatible , Tri-state output
•
Common I/O capability
•
Automatic power-down when deselected
•
Available in 32-pin SOP ,TSOP-I(8x20mm),
TSOP-I(8x13.4mm) ,48-pin CSP packages
•
Operating temperature :
Commercial :
Industrial :
0 ~ +70
°C
-40 ~ +85
°C
128K X 8 LOW POWER
CMOS STATIC RAM
GENERAL DESCRIPTION
The T15N1024A is a very Low Power CMOS
Static RAM organized as 131,072 words by 8 bits.
That operates on a wide voltage range from 2.4V
to 3.6V power supply, Fabricated using high
performance
CMOS
technology,
Inputs
and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures. Data retention is guaranteed at a power
supply voltage as low as 1.5V.
BLOCK DIAGRAM
PART NUMBER EXAMPLES
PART NO.
T15N1024A-55D
T15N1024A-70H
T15N1024A-100P
T15N1024A-100C
T15N1024A-55DI
T15N1024A-70HI
T15N1024A-100PI
T15N1024A-100CI
PACKAGE
CODE
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
C=CSP
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
C=CSP
Operating
Temperature
0 ~ +70
°C
Vcc
Vss
A0
.
.
.
A16
WE
OE
CE1
CE2
DECODER
CORE
ARRAY
-40 ~ +85
°C
CONTROL
CIRCUIT
DATA I/O
I/O1
..
I/O8
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: FEB. 2003
Revision:E
TMT [ TAIWAN MEMORY TECHNOLOGY ]
