tm
A d d re s s
C E 1
TE
CH
(
WE
Controlled)
t
W
C
T15N1024A
WRITE CYCLE 1
t
A
t
C
W
W
t
W
R
C E 2
t
A
W E
t
O
t
W
D
o u t
H Z
W
S
t
W
P
H ig h - Z
t
D
W
t
D
H
D
IN
H ig h - Z
D O N 'T C A R E
U N D E F IN E D
WRITE CYCLE 2
A d d re s
s
( CE Controlled)
t
W
C
t
A W
t
C W
t
W
R
C E 1
t
A S
C E 2
t
W
W E
P
D
out
H ig h - Z
t
D
W
t
D
H
D
IN
H ig h - Z
D O N 'T C A R E
U N D E F IN E D
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low
CE
1
, a high CE2 and a low WE . A write begins at
the lateat transition among
CE
1
goes low, CE2 going high and WE going low. A write end at
the earliest transition among
CE
1
going high, CE2 going low and WE going high. tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the later of
CE
1
going low or CE2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
TM Technology Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: FEB. 2003
Revision:E
TMT [ TAIWAN MEMORY TECHNOLOGY ]
