tm
TE
CH
T221160A
DRAM
FEATURES
64K x 16 DYNAMIC RAM
FAST PAGE MODE
PIN ASSIGNMENT ( Top View )
V cc
I/01
I/02
I/03
I/04
V cc
I/05
I/06
I/07
I/08
NC
NC
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
V ss
I/016
I/015
I/014
I/013
V ss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
NC
A7
A6
A5
A4
VSS
•
High speed access time : 25/30/35/40 ns
•
Industry-standard x 16 pinouts and timing
functions.
•
Single 5V (±10%) power supply.
•
All device pins are TTL- compatible.
•
256-cycle refresh in 4ms.
•
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
•
Conventional FAST PAGE MODE access cycle.
•
BYTE WRITE and BYTE READ access cycles.
SO J
31
30
29
28
27
26
25
24
23
22
21
PART NUMBER EXAMPLES
PART NUMBER
R AS
NC
A0
A1
ACCESS TIME
30ns
30ns
35ns
35ns
PACKAGE
SOJ
TSOP-II
SOJ
TSOP-II
T221160A-30J
T221160A-30S
T221160A-35J
T221160A-35S
A2
A3
V cc
V cc
I/01
1
2
3
4
5
6
7
8
9
10
T S O P (II)
40
39
38
37
36
35
34
33
32
31
V ss
I/01 6
I/01 5
I/01 4
I/01 3
V ss
I/01 2
I/01 1
I/01 0
I/09
GENERAL DESCRIPTION
The T221160A is a randomly accessed solid state
memory containing 1,048,551 bits organized in a
x16 configuration. The T221160A has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode operation
The T221160A CAS function and timing are
I/02
I/03
I/04
V cc
I/05
I/06
I/07
I/08
NC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
CA SL
CA SH
OE
NC
A7
A6
A5
A4
V SS
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (IO1~IO8), and CASH
transiting low will write data into the upper byte
(IO9~16).
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
NC
WE
RAS
NC
A0
A1
A2
A3
V cc
Publication Date: FEB. 2002
Revision:A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
