tm
TE
CH
T224162B
DRAM
256K x 16 DYNAMIC
RAM
EDO PAGE MODE
FEATURES
•
Industry-standard x 16 pinouts and timing
functions.
•
Single 5V (
±
10%) power supply.
•
All device pins are TTL- compatible.
•
512-cycle refresh in 8ms.
•
Refresh modes: RAS only, CAS BEFORE
RAS
(CBR) and HIDDEN.
•
Extended data-out (EDO) PAGE MODE
access cycle.
•
BYTE WRITE and BYTE READ access
cycles.
PIN ASSIGNMENT ( Top View )
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
1
2
3
4
5
6
7
8
9
10
TSOP(II)
NC
NC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
40
39
38
37
36
35
34
33
32
31
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
OPTION
TIMING
22ns
25ns
28ns
35ns
45ns
50ns
EDO
125 MHz
100 MHz
100 MHz
83 MHz
60 MHz
50 MHz
MARKING
J
S
MARKING
-22
-25
-28
-35
-45
-50
WE
RAS
NC
A0
A1
A2
A3
Vcc
PACKAGE
SOJ
TSOP(II)
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS pins. It offers Fast Page mode with Extended
Data Output.
The T224162B
CAS
function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high during
WRITE will result in a BYTE WRITE.
CASL
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and CASH transiting low
will write data into the upper byte (IO9~16).
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SOJ
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
Publication Date: AUG. 2000
Revision:L
TMT [ TAIWAN MEMORY TECHNOLOGY ]
