tm
TE
CH
T35L6464A
SYNCHRONOUS
BURST SRAM
FEATURES
•
Fast Access times: 5, 6, 7, and 8ns
•
Fast clock speed: 100, 83, 66, and 50 MHz
•
Provide high performance 3-1-1-1 access rate
•
Fast OE access times: 5 and 6ns
•
Single 3.3V +10% / -5V power supply
•
Common data inputs and data outputs
•
BYTE WRITE ENABLE and GLOBAL
WRITE control
•
Five chip enables for depth expansion and
address pipelining
•
Address, control, input, and output pipelined
registers
•
Internally self -timed WRITE cycle
•
WRITE pass-through capability
•
Burst control pins ( interleaved or linear burst
sequence)
•
High density, high speed packages
•
Low capacitive bus loading
•
High 30pF output drive capability at rated access
time
•
SNOOZE MODE for reduced power standby
•
Single cycle disable ( Pentium
T M
BSRAM
compatible )
64K x 64 SRAM
3.3V SUPPLY, FULLY REGISTERED AND OUTPUTS,
BURST COUNTER
PIN ASSIGNMENT
(Top View)
128127126125 124 123122 121 120 119 118117 116115114113112111110109108107106105104103
VSSQ
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
VCCQ
VSSQ
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
VCCQ
VSSQ
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSS
VCC
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
VSS
VCC
BW2
BW1
ADSC
ADSP
ADV
VSSQ
VCCQ
CE3
CE2
CE3
CE2
128-pin QFP
or
128-pin LQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
VSSQ
VCCQ
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
VSSQ
VCCQ
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
VSSQ
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VSSQ
NC
MODE
A15
A14
A13
VCC
VSS
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VCC
VSS
A2
A1
A0
ZZ
VCCQ
OPTIONS
TIMING
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
128-pin QFP
128-pin LQFP
MARKING
-5
-6
-7
-8
Q
L
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6464A SRAM integrates 65536 x 64
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, three active LOW
chip enable (CE , CE2 and CE3 ), two additional
chip enables (CE2 and CE3) , burst control inputs
Publication Date: AUG. 1998
Revision: E
Part Number Examples
PART NO.
T35L6464A -5Q
T35L6464A -5L
Pkg.
Q
L
BURST SEQUENCE
Interleaved
(MODE=NC or VCC)
Linear (MODE=GND)
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
TMT [ TAIWAN MEMORY TECHNOLOGY ]
