tm
TE
CH
T436416A
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
Symbol
-6
12
16
18
42
60
Speed Version
-7 -7.5 -8
14
18
20
42
63
15
18
20
45
100K
65
1
2
1
1
1
1
68
16
20
20
48
-10
20
20
20
50
70
Unit
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2
2
2
3
4
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
CAS latency=2
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is
CL + BL-2 clocks.
TM Technology Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
