tm
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TE
CH
T436416C
SDRAM
FEATURES
3.3V power supply
Four banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
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DQM for masking
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Auto refresh and self refresh
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64ms refresh period
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15.6 us refresh interval.
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MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
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Available package type in 54 pin TSOP(II)
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Operating temperature : 0 ~ +70
°C
4M x 16 SDRAM
1M x 16bit x 4Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T436416C is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 1,048,576 words by 16 bits , fabricated with
high performance CMOS technology .
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable burst length and
programmable latencies allow the same device to
be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
PART NO.
MAX
FREQUENCY
PACKAGE
PIN ARRANGEMENT (Top
View)
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
5 4 P IN T S O P ( II)
( 4 0 0 m il x 8 7 5 m il)
( 0 .8 m m P IN P IT C H )
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V ss
D Q 15
V
SSQ
DQ0
V
DDQ
T436416C-6S
T436416C-7S
T436416C-6SG
T436416C-7SG
166 MHz
143 MHz
166 MHz
143 MHz
54 pin TSOP(II)
54 pin TSOP(II)
54 pin TSOP(II)
lead-free
54 pin TSOP(II)
lead-free
DQ1
DQ2
V
SSQ
D Q 14
D Q 13
V
DDQ
DQ3
DQ4
V
DDQ
D Q 12
D Q 11
V
SSQ
DQ5
DQ6
V
SSQ
D Q 10
DQ9
V
DDQ
DQ7
V
DD
DQ8
V ss
N .C / R F U
UDQM
CLK
CKE
N .C
A 11
A9
A8
A7
A6
A5
A4
V ss
LDQM
W E
CAS
RAS
CS
A 13
A 12
A 1 0 /A P
A0
A1
A2
A3
V
DD
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
TMT [ TAIWAN MEMORY TECHNOLOGY ]
